High density SRAM cell with latched vertical transistors
AssigneeMicron Technology, Inc.
InventorsWendell P. Noble JR., Leonard Forbes
Life of this patent
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Abstract
High density static memory cells and arrays containing gated lateral bipolar transistors which can be latched in a bistable on state. Each transistor memory cell includes two gates which are pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.
Claims54
A memory cell, comprising gated lateral bipolar transistors and having bistable current states for storing information, one of said current states being achieved by operation of gate-induced latchup of said transistors.
A circuit for storing information as one of at least two possible bistable current states, comprising
- at least one vertical p-n-p-n structure containing a bipolar p-n-p transistor merged with a bipolar n-p-n transistor;
- a transistor gate in connection with the n-region of said p-n-p transistor;
- and
- a transistor gate in connection with the p-region of said n-p-n transistor.
A SRAM cell, comprising:
- a p-n-p-n transistor having a first p-region, a first n-region, a second p-region, and a second n-region;
- and
- a first gate in connection with the first n-region, and a second gate in connection with said second p-region, wherein said gates are connected to at least one voltage source for producing latch-up in said p-n-p-n transistor as one of the bistable current states for storing information in said SRAM cell.
A SRAM array, comprising
- a substrate;
- a plurality of vertical p-n-p-n transistors;
- a first set of isolation trenches between said p-n-p-n transistors for isolating said transistors in a first direction;
- a second set of isolation trenches orthogonal to said first set of trenches for isolating said transistors in a second direction;
- a gate line in at least some of said trenches of said first set of trenches and connecting the n-regions of at least some of said plurality of transistors;
- and
- a gate line in at least some of said trenches of said second set of trenches and connecting the p-regions of at least some of said plurality of transistors.
A computer system, comprising
- a processor;
- and
- a memory circuit connected to the processor, the memory circuit containing at least one memory cell comprising two gated complementary bipolar transistors and having bistable current states for storing information, one of said current states being achieved by operation of gate-induced latch-up of said transistors, wherein the complementary bipolar transistors comprise a vertical p-n-p transistor and a vertical n-p-n transistor and the collector region of said p-n-p transistor is connected with the base region of said n-p-n transistor.
The computer system of claim 33 wherein said p-n-p transistor has a gate in connection with the n-region of said transistor, and said n-p-n transistor has a gate in connection with the p-region of said transistor.
A method of forming a memory cell for storing information as one of at least two possible bistable current states, the method comprising the following steps:
- providing a semiconductor substrate;
- providing doped silicon regions in the following doping profile:
- p, n, p and n, to form a vertical p-n-p-n transistor;
- forming a p-type polysilicon gate in connection with the n-region of said transistor;
- and
- forming an n-type polysilicon gate in connection with the p-region of said transistor.
A semiconductor processing method of forming CMOS static access memory within a semiconductor substrate, the method comprising the following steps:
- providing a semiconductor substrate;
- defining an array trench within said substrate;
- providing doped silicon in said trench in the following doping profile:
- p, n, p and n;
- defining a first set of trenches in said doped silicon by directional etching to a depth at least sufficient to expose the buried p-type layer;
- defining a second set of trenches orthogonal to said first set of trenches by directional etching to a depth at least sufficient to expose the buried p-type layer;
- growing a gate oxide layer on at least one of the sidewalls of each trench of said first and second sets of trenches;
- and
- defining a p-type polysilicon gate within each trench of one of said sets of trenches and in connection with the n-regions of said doped silicon, and an n-type polysilicon gate within each trench of said other set of trenches and in connection with the p-regions of said doped silicon.
A semiconductor processing method of forming CMOS static access memory within a semiconductor substrate, the method comprising the following steps:
- providing a semiconductor substrate;
- defining an array trench within said substrate;
- providing doped silicon in said trench in the following doping profile:
- p, n, p and n;
- defining a first set of trenches in said doped silicon by directional etching to a depth at least sufficient to expose the buried p-type layer;
- defining a second set of trenches orthogonal to said first set of trenches by directional etching to a depth at least sufficient to expose the buried p-type layer;
- growing a gate oxide layer on at least one of the sldewalls of each trench of said first and second sets of trenches;
- depositing a p-type polysilicon layer in the first set of trenches;
- removing said p-type polysilicon layer, while leaving remaining polysilicon as p-type gate material on one sidewall of each trench of said first set of trenches and in connection with the n-regions of said doped polysilicon;
- depositing an n-type polysilicon layer in the second set of trenches;
- removing said n-type polysilicon layer, while leaving remaining polysilicon as n-type gate material on one sidewall of each trench of said second set of trenches and in connection with the p-regions of said doped polysilicon;
- and
- depositing oxide to fill the trenches of said first and second sets of trenches.
A method of storing a binary logic value comprising:
- inducing latch-up in a gated diode.
A method of forming a circuit for storing information as one of at least two possible stable current states, the method comprising the following steps:
- providing a semiconductor substrate;
- providing doped silicon regions to form a multi-region vertical thyristor having at least four regions;
- forming at least two polysilicon gates in connection with at least two separate junctions of said multi-region vertical thyristor;
- and
- connecting said at least two polysilicon gates to a voltage source for producing latch-up in said multi-region vertical thyristor.
Dependencies are inferred from the claim text.