Novel masked nitrogen enhanced gate oxide

A method for fabricating an integrated circuit device including N-channel and P-channel devices having selectively hardened gate oxides on a substrate, the method comprising:

• forming an oxide layer over at least a portion of the substrate;
• forming a first resist over at least a portion of the oxide layer;
• patterning the first resist to create at least one exposed area of the oxide layer and at least one covered area of the oxide layer;
• conducting a first remote plasma nitrogen treatment to create at least one partially hardened area within the oxide layer and at least one non-hardened area within the oxide layer;
• stripping the first resist;
• growing at least a portion of the at least one non-hardened area within the oxide layer using a thermal oxidation process to form at least one thick area within the oxide layer;
• forming a second resist over at least a portion of the at least one thick area within the oxide layer;
• patterning the second resist to create at least one exposed area of the at least one thick area;
• and
• conducting a second remote plasma nitrogen treatment to create at least one second hardened area and at least one second non-hardened area within the at least one thick area of the oxide layer.

A method for fabricating an integrated circuit device including N-channel and P-channel devices on a substrate, each N-channel and P-channel device having selectively hardened gate oxides, the method comprising:

• forming an oxide layer over at least a portion of the substrate;
• forming a first resist over at least a portion of the oxide layer;
• patterning the first resist to create at least one exposed area of the oxide layer and at least one covered area of the oxide layer;
• conducting a first remote plasma nitrogen hardening treatment to create at least one partially hardened area within the oxide layer and at least one non-hardened area within the oxide layer;
• stripping the first resist;
• growing at least a portion of the at least one non-hardened area within the oxide layer using a thermal oxidation process to form at least one thick area within the oxide layer;
• forming a second resist over at least a portion of the at least one thick area within the oxide layer;
• patterning the second resist to create at least one exposed area of the at least one thick area;
• and
• conducting a second remote plasma nitrogen hardening treatment to create at least one second hardened area and at least one second non-hardened area within the at least one thick area of the oxide layer.

A method for fabricating a dynamic random access memory device on a substrate comprising:

• forming an oxide layer over at least a portion of the substrate;
• forming a resist over at least a portion of the oxide layer;
• patterning the resist to create at least one exposed area of the oxide layer;
• partially hardening the at least one exposed area of the oxide layer using a remote plasma nitrogen hardening treatment;
• processing the substrate and the oxide layer to create at least one P-channel device having a hardened oxide and an array of N-channel devices, each of the N-channel devices included within the array having a non-hardened gate oxide;
• forming a second resist over at least a portion within the oxide layer;
• patterning the second resist to create at least one exposed area of the oxide layer;
• and
• conducting a second remote plasma nitrogen hardening treatment to create at least one second hardened area and at least one non-hardened area within the oxide layer.

A method for hardening at least a portion of a gate oxide layer on a substrate, comprising:

• forming an oxide layer over at least a portion of the substrate;
• forming a resist over at least a portion of the oxide layer;
• patterning the resist to create at least one exposed area of the oxide layer;
• partially hardening the at least one exposed area of the oxide layer using a remote plasma nitrogen hardening treatment forming a partially hardened oxide layer having a first thickness;
• forming a second resist over at least a portion of the oxide layer;
• patterning the second resist to create at least one exposed area of the oxide layer;
• and
• conducting a second remote plasma nitrogen hardening treatment to create at least one second hardened area having a second thickness and at least one non-hardened area within the oxide layer.

A method for fabricating an integrated circuit device including N-channel and P-channel devices having selectively hardened gate oxides on a substrate, the method comprising:

• forming an oxide layer over at least a portion of the substrate;
• forming a first resist over at least a portion of the oxide layer;
• patterning the first resist to create at least one exposed area of the oxide layer and at least one covered area of the oxide layer;
• conducting a first remote plasma nitrogen treatment to create at least one partially hardened area within the oxide layer having a first thickness and at least one non-hardened area having a first thickness within the oxide layer;
• stripping the first resist;
• growing at least a portion of the at least one non-hardened area within the oxide layer using a thermal oxidation process to form at least one thick area within the oxide layer;
• forming a second resist over at least a portion of the at least one thick area within the oxide layer;
• patterning the second resist to create at least one exposed area of the at least one thick area;
• and
• conducting a second remote plasma nitrogen treatment to create at least one second hardened area having another thickness and at least one second non-hardened area within the at least one thick area of the oxide layer.

A method for fabricating an integrated circuit device including N-channel and P-channel devices on a substrate, each N-channel and P-channel device having selectively hardened gate oxides, the method comprising:

• forming an oxide layer over at least a portion of the substrate;
• forming a first resist over at least a portion of the oxide layer;
• patterning the first resist to create at least one exposed area of the oxide layer and at least one covered area of the oxide layer;
• conducting a first remote plasma nitrogen hardening treatment to create at least one partially hardened area within the oxide layer having a first thickness and at least one non-hardened area within the oxide layer;
• stripping the first resist;
• growing at least a portion of the at least one non-hardened area within the oxide layer using a thermal oxidation process to form at least one thick area within the oxide layer having a second thickness;
• forming a second resist over at least a portion of the at least one thick area within the oxide layer;
• patterning the second resist to create at least one exposed area of the at least one thick area;
• and
• conducting a second remote plasma nitrogen hardening treatment to create at least one second hardened area and at least one second non-hardened area within the at least one thick area of the oxide layer.

A method for fabricating a dynamic random access memory device on a substrate comprising:

• forming an oxide layer over at least a portion of the substrate;
• forming a resist over at least a portion of the oxide layer;
• patterning the resist to create at least one exposed area of the oxide layer having a first thickness;
• partially hardening the at least one exposed area of the oxide layer using a remote plasma nitrogen hardening treatment;
• processing the substrate and the oxide layer to create at least one P-channel device having a hardened oxide and an array of N-channel devices, each of the N-channel devices included within the array having a non-hardened gate oxide;
• forming a second resist over at least a portion within the oxide layer;
• patterning the second resist to create at least one exposed area of the oxide layer;
• and
• conducting a second remote plasma nitrogen hardening treatment to create at least one second hardened area having a second thickness and at least one non-hardened area within the oxide layer.