Anti-type dosage as LDD implant
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShu-Ying Cho, Chien-Chung Wang, Chien-Ming Chung, Yuan-Chang Huang
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Abstract
A method is provided for turning off MOS transistors through an anti-code (type) LDD implant without the need for high energy implant that causes poly damage. The method also negates any deleterious effects due to the variations in the thickness of the poly gate. The anti-code LDD implant can be performed vertically, or at a tilt angle, or in a combination of vertical and tilt angle. The method can be made part of a Flash-ROM process that is applicable to both polycide and silicide processes.
Claims36
A method of using anti-code dosage as LDD implant to turn off a MOS transistor comprising the steps of:
- providing a substrate having an NMOS region and a PMOS region;
- forming a dielectric layer over said substrate, including over said NMOS and PMOS regions;
- forming an NMOS gate electrode over said NMOS region and a PMOS gate electrode over said PMOS region over said dielectric layer formed over said NMOS and PMOS regions;
- forming a first cover layer over said PMOS region including over said PMOS gate electrode;
- performing an N-type lightly doped drain (NLDD) implant over uncovered said NMOS region using said NMOS gate electrode as a self-aligned mask;
- removing said first cover layer from over said PMOS region;
- forming a second cover layer over said NMOS region including over said NMOS gate electrode;
- performing P-type lightly doped drain (PLDD) implant over uncovered said PMOS region using said PMOS gate electrode as a self-aligned mask;
- removing said second cover layer from over said NMOS region;
- forming a third cover layer over said PMOS region including over said PMOS gate electrode;
- performing a code implant over uncovered said NMOS region using said NMOS gate electrode as a self-aligned mask;
- removing said third cover layer from over said PMOS region;
- forming a fourth cover layer over said NMOS region including over said NMOS gate electrode;
- performing a code implant over uncovered said PMOS region using said PMOS gate electrode as a self-aligned mask;
- removing said fourth cover layer from over said NMOS region;
- and
- performing a vertical anti-code LDD implant to turn off said MOS transistor.
The method according to claim 13, wherein said substrate is silicon.
The method according to claim 13, wherein said dielectric layer is a gate oxide layer having a thickness between about 100 to 150 angstroms (Å).
The method according to claim 13, wherein said NMOS and PMOS gate electrodes comprise a polysilicon layer having a thickness between about 1400 to 1600 Å, a tetraethyl orthosilicate (TEOS) layer having a thickness between about 750 to 850 Å, and a tungsten silicide layer having a thickness between about 1000 to 1500 Å.
The method according to claim 13, wherein said NMOS and PMOS gate electrodes comprise polycide which further comprises polysilicon having a thickness between about 1400 to 1600 Å and tungsten silicide having a thickness between about 1200 to 1300 Å.
The method according to claim 13, wherein said first cover layer is photoresist having a thickness between about 1.0 to 1.2 micrometers (μm).
A method of using anti-code dosage as LDD implant to turn off a MOS transistor comprising the steps of:
- providing a substrate having an NMOS region and a PMOS region;
- forming a dielectric layer over said substrate, including over said NMOS and PMOS regions;
- forming an NMOS gate electrode over said NMOS region and a PMOS gate electrode over said PMOS region over said dielectric layer formed over said NMOS and PMOS regions;
- forming a first cover layer over said PMOS region including over said PMOS gate electrode;
- performing an N-type lightly doped drain (NLDD) implant over uncovered said NMOS region using said NMOS gate electrode as a self-aligned mask;
- removing said first cover layer from over said PMOS region;
- forming a second cover layer over said NMOS region including over said NMOS gate electrode;
- performing P-type lightly doped drain (PLDD) implant over uncovered said PMOS region using said PMOS gate electrode as a self-aligned mask;
- removing said second cover layer from over said NMOS region;
- forming a third cover layer over said PMOS region including over said PMOS gate electrode;
- performing a code implant over uncovered said NMOS region using said NMOS gate electrode as a self-aligned mask;
- removing said third cover layer from over said PMOS region;
- forming a fourth cover layer over said NMOS region including over said NMOS gate electrode;
- performing a code implant over uncovered said PMOS region using said PMOS gate electrode as a self-aligned mask;
- removing said fourth cover layer from over said NMOS region;
- and
- performing a tilt angle anti-code LDD implant to turn off said MOS transistor.
A method of using anti-code dosage as LDD implant to turn off a MOS transistor comprising the steps of:
- providing a substrate having an NMOS region and a PMOS region;
- forming a dielectric layer over said substrate, including over said NMOS and PMOS regions;
- forming an NMOS gate electrode over said NMOS region and a PMOS gate electrode over said PMOS region over said dielectric layer formed over said NMOS and PMOS regions;
- forming a first cover layer over said PMOS region including over said PMOS gate electrode;
- performing an N-type lightly doped drain (NLDD) implant over uncovered said NMOS region using said NMOS gate electrode as a self-aligned mask;
- removing said first cover layer from over said PMOS region;
- forming a second cover layer over said NMOS region including over said NMOS gate electrode;
- performing P-type lightly doped drain (PLDD) implant over uncovered said PMOS region using said PMOS gate electrode as a self-aligned mask;
- removing said second cover layer from over said NMOS region;
- forming a third cover layer over said PMOS region including over said PMOS gate electrode;
- performing a code implant over uncovered said NMOS region using said NMOS gate electrode as a self-aligned mask;
- removing said third cover layer from over said PMOS region;
- forming a fourth cover layer over said NMOS region including over said NMOS gate electrode;
- performing a code implant over uncovered said PMOS region using said PMOS gate electrode as a self-aligned mask;
- removing said fourth cover layer from over said NMOS region;
- and
- performing a vertical and tilt angle anti-code LDD implant to turn off said MOS transistor.
Dependencies are inferred from the claim text.