Fully differential CMOS phase-locked loop

A phase-locked loop comprising:

• a detector configured to receive a differential input signal and a differential reference signal and to provide a differential detector output signal indicative of a difference between the differential input signal and the differential reference signal;
• a Gm cell circuit coupled to the detector and configured to receive the differential detector output signal and to provide a differential current output signal;
• a signal filter coupled to the Gm cell circuit and configured to receive the differential current output signal and to provide a differential control signal;
• and
• a voltage controlled oscillator coupled to the signal filter and configured to receive the differential control signal and to provide a differential oscillator signal which is adjustable based on the differential control signal, the differential oscillator signal is fed back to the detector as the differential input signal;
• wherein the detector, the GM cell circuit, the signal filter, and the voltage controlled oscillator are each implemented using C3MOS logic.

A phase-locked loop comprising:

• a detector configured to receive an input signal and a reference signal and to provide a detector output signal indicative of a difference between the input signal and the reference signal;
• a Gm cell circuit coupled to the detector and configured to receive the detector output signal and to provide a current output signal;
• a signal filter coupled to the Gm cell circuit and configured to receive the current output signal and to provide a control signal;
• a voltage controlled oscillator coupled to the signal filter and configured to receive the control signal and to provide an oscillator signal which is adjustable based on the control signal;
• and
• a divider circuit coupled to the voltage controlled oscillator and configured to receive the oscillator signal and to provide a divided version of the oscillator signal to be fed to the detector as the input signal;
• wherein the detector, the Gm cell circuit, the signal filter, the voltage controlled oscillator and the divider circuit are connected to one another in a fully differential manner;
• and
• wherein the detector, the Gm cell circuit, the signal filter, the voltage controlled oscillator and the divider circuit are implemented using C3MOS logic.

A method for implementing a phase-locked loop, comprising:

• providing a differential input signal and a differential reference signal to a detector;
• providing a differential detector output signal from the detector as input to a signal filter;
• providing a differential control signal from the signal filter as input to a voltage controlled oscillator;
• and
• providing a differential oscillator signal from the voltage controlled oscillator as the input signal to the detector.

A method for implementing a phase-locked loop, comprising:

• providing a differential input signal and a differential reference signal to a detector;
• providing a differential detector output signal from the detector as input to a Gm cell circuit;
• providing a differential current output signal from the Gm cell circuit as input to a signal filter;
• providing a differential control signal from the signal filter as input to a voltage controlled oscillator;
• providing a differential oscillator signal from the voltage controlled oscillator as input to a divider circuit;
• providing a divided version of the differential oscillator signal from the divider circuit as the differential input signal to the detector;
• and
• implementing the detector, the Gm cell circuit, the signal filter, the voltage controlled oscillator and the divider circuit using C3MOS logic.