Receiver for clock and data recovery and method for calibrating sampling phases in a receiver for clock and data recovery

Abstract

The receiver for clock and data recovery according to the invention comprises n sampling latches (SL1 . . . SLn) for determining n sample values (SV1 . . . SVn) of a reference signal (Ref2) at n sampling phases (φ1a . . . (φna) having sampling latch inputs and sampling latch outputs. The receiver further comprises a phase position analyzer (5) connected to said sampling latch outputs for generating an adjusting signal (AS) for adjusting the sampling phase (φ1a . . . (φna), if the sample value (SV1 . . . SVn) deviates from a set point and a phase interpolator (9) for generating sampling phases (φ1u . . . (φnu). A sampling phase adjusting unit (6) connected with its inputs to the phase position analyzer (5) and the phase interpolator (9) and with its outputs to the sampling latches (SL1 . . . SLn) is provided for generating adjusted sampling phases (φ1a . . . (φna) depending on said sampling phases (φ1u . . . (φnu) and said adjusting signal (AS).

Dependencies are inferred from the claim text.