Method and system for fast timing recovery for preamble based transmission systems

A method of timing synchronization to a symbol boundary of a packet conforming to an IEEE 802.11 standard occurring at a network access point comprising:

• detecting a rise in short power, wherein the incoming power of a signal is above a set threshold for a set number of consecutive clock cycles;
• in response to detection of a rise in short power, performing an auto-correlation on samples of an incoming packet to identify the preamble and a first approximation of a trailing boundary of the preamble;
• and
• performing a cross-correlation between samples of an incoming packet and a standard preamble and processing the results by discarding a number of the most recent cross-correlation values, locating a number of maximum peaks in the remaining cross-correlation values, then repeatedly selecting a maximum peak occurring earliest in time as the symbol timing boundary unless any of the remaining maximum peaks occurs a certain distance of cross-correlation values or more away, until a maximum peak has been identified as a symbol timing boundary near the first approximation.

An apparatus for timing synchronization to a symbol boundary of a packet comprising:

• an auto-correlator that performs an auto-correlation on samples of an incoming packet;
• a cross-correlator that performs a cross-correlation between samples of the incoming packet and standard symbol values;
• and
• a processor with inputs from both the auto-correlator and the cross-correlator, wherein the processor first identifies a first approximation of a trailing boundary of the symbol using the input from the auto-correlator, and subsequently more precisely identifies the symbol timing boundary near the first approximation using the input from the cross-correlator.

An apparatus located in network access point for timing synchronization to a symbol boundary of a packet conforming to an IEEE 802.11 standard comprising:

• a delay line, the delay line having a plurality of pipelined registers for receiving samples of an incoming packet;
• an auto-correlator connected to registers of the delay line that performs an auto-correlation on samples of an incoming packet;
• a cross-correlator connected to registers of the delay line that performs a cross-correlation between samples of the incoming packet and standard preamble values, and includes a peak processing module for discarding a number of the most recent cross-correlation values, locating a number of maximum peaks in the remaining cross-correlation values and determining the symbol trailing boundary depending on the distance between the maximum peaks, and then repeatedly selecting a maximum peak occurring earliest in time as the symbol timing boundary unless any of the remaining maximum peaks occurs a certain distance of cross-correlation values or more away, until a maximum peak has been identified as a symbol timing boundary;
• a short power circuit connected to the registers of the delay line that detects a rise in short power, where a rise is determined when the incoming power of a packet is above a set threshold for a set number of consecutive data samples;
• and
• a processor with inputs from the auto-correlation circuit, the cross-correlation circuit, and the short power circuit, wherein the processor initiates the performance of the auto-correlation circuit when prompted by the short power circuit, then identifies a first approximation of a trailing boundary of the preamble using the input from the auto-correlation circuit, and subsequently more precisely identifies the symbol timing boundary near the first approximation using the input from the cross-correlation circuit.