Reconfigurable fir filter

A finite impulse response (FIR) filter for filtering an input digital signal according to a function defined by a series of coefficients, the FIR filter comprising:

• a series of connected digit processing units (DPUs), a first DPU of the series receiving the input digital signal, each DPU comprising:
• a delay unit receiving the input digital signal from an input of the FIR filter or from the previous DPU for storing and delaying the input digital signal;
• a multiplexer capable of selecting a delayed digital input signal from the delay unit or an un-delayed digital input signal bypassing the delay unit, an output of the multiplexer for connecting to a delay unit and a multiplexer of a next stage DPU;
• and
• a coefficient multiplier connected to the output of the delay unit for multiplying the input digital signal by a coefficient and outputting a product;
• an adder connected to the coefficient multipliers for summing the products of the coefficient multipliers, wherein the adder outputs the filtered digital signal;
• wherein a group of DPUs having multiplexers set so that the delay unit of each DPU stores the same part of the digital signal process a single coefficient of the series of coefficients.

A processing element for filtering an input digital signal according to a function defined by a series of coefficients, the processing element comprising:

• a series of connected digit processing units (DPUs), a first DPU of the series receiving the input digital signal, each DPU comprising:
• a delay unit receiving the input digital signal from an input of the processing unit or from the previous DPU for storing and delaying the input digital signal;
• a multiplexer capable of selecting a delayed digital input signal from the delay unit or an un-delayed digital input signal bypassing the delay unit, an output of the multiplexer for connecting to a delay unit and a multiplexer of a next stage DPU;
• a coefficient multiplier connected to the output of the delay unit for multiplying the input digital signal by a coefficient and outputting a product;
• and
• a serial-in-parallel-out (SIPO) shift register capable of serially receiving control signals and outputting control signals to the coefficient multiplier and the multiplexer;
• an adder connected to the coefficient multipliers for summing the products of the coefficient multipliers, wherein the adder outputs the filtered digital signal;
• a second register connected to the adder for storing a number of negative products determined by the coefficient multipliers for performing two's complement arithmetic with the adder;
• and
• a sign extension generator connected to the adder for generating sign extension bits of the products of the coefficient multipliers;
• wherein a group of DPUs having multiplexers set so that the delay unit of each DPU stores the same part of the digital signal process a single coefficient of the series of coefficients.

A method for filtering an input digital signal according to a function defined by a series of coefficients, the method comprising:

• serially receiving the input digital signal as a series of equal length elements;
• simultaneously multiplying each element of the serially received digital signal by a corresponding coefficient of the series of coefficients;
• adding the products of the multiplications;
• and
• outputting the sum of the products of the multiplications as the filtered digital signal.