Enhanced rake structure
AssigneeInterDigital Technology Corporation
InventorWilliam C. Hackett
Life of this patent
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Abstract
A rake architecture for a frequency division duplex (FDD) and use also in TDD and TD-SCDMA type communications system, designed to significantly reduce the memory capacity required and thereby also reduce an area on the die of an application specific integrated circuit (ASIC) into which the memory is integrated. A single circular buffer, preferably of the shared memory type is shared by all of the rake fingers of a rake receiver to significantly reduce the hardware and software required to time align multipath signals received by a UE from a base station. This unique time alignment technique also reduces the number of code generators required to track a plurality (typically three) of base stations.
Claims2
A method for providing time alignment of multipath signals received by a rake receiver from a given base station, said rake receiver having a plurality of rake fingers, comprising:
- receiving encoded multipath signals from said base station;
- writing said signals into a given location in a shared memory;
- reading said signals from a location in the shared memory offset from the write-in location responsive to a given chip offset so that the signals are time aligned when read out of the shared memory.
Dependencies are inferred from the claim text.