System and method for establishing a known timing relationship between two clock signals
AssigneeHewlett-Packard Development Company, L.P.
InventorRajakrishnan Radjassamy
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Abstract
A system and method for establishing a known timing relationship between two clock signals, wherein a first clock signal is operable to clock data transfer operations from a transmitter domain to a receiver domain and a second clock signal is operable to be transported to the receiver domain. Circuitry is provided for detecting an edge in a global framework clock (GFC) signal that is supplied to the transmitter domain. A common alignment signal is manufactured that is based at least in part upon the GFC signal. A multiplexer and register arrangement is operable to output the second clock signal in response to the common alignment signal which is also used for gating the data transfer operations clocked by the first clock signal.
Claims25
A system for establishing a known timing relationship between two clock signals, wherein a first clock signal is operable to clock data transfer operations from a transmitter domain to a receiver domain and a second clock signal is operable to be transported to said receiver domain, comprising:
- means for detecting an edge in a global framework clock (GFC) signal that is supplied to said transmitter domain;
- means for manufacturing a common alignment signal that is derived at least in part from said GFC signal;
- and
- a multiplexer arrangement operating to output said second clock signal in response to said common alignment signal, wherein said data transfer operations are gated with said common alignment signal.
A method for establishing a known timing relationship between two clock signals, wherein a first clock signal is operable to clock data transfer operations from a transmitter domain to a receiver domain and a second clock signal is operable to be transported to said receiver domain, comprising:
- detecting an edge in a global framework clock (GFC) signal that is supplied to said transmitter domain;
- manufacturing a common alignment signal that is at least in part derived from said GFC signal;
- and
- using said common alignment signal for gating said data transfer operations and for controlling a multiplexer arrangement in outputting said second clock signal.
A computer system provided with circuitry for establishing a known timing relationship between two clock signals, wherein a first clock signal is operable to clock data transfer operations from a transmitter domain to a receiver domain and a second clock signal is operable to be transmitted to said receiver domain, said transmitter and receiver domains forming at least a portion of said computer system, said circuitry comprising:
- a register operating responsive to said first clock signal for detecting an edge in a global framework clock (GFC) signal that is supplied to said transmitter domain;
- means for manufacturing a common alignment signal that is derived at least in part from said GFC signal;
- and
- a multiplexer arrangement operating to output said second clock signal in response to said common alignment signal, wherein said data transfer operations are gated with said common alignment signal.
A circuit for establishing a known timing relationship between two clocks, wherein a first clock signal is operable to clock data transfer operations from a transmitter domain to a receiver domain and a second clock signal is operable to be transported to said receiver domain, comprising:
- a register operating responsive to said first clock signal for detecting an edge in a global framework clock (GFC) signal that is supplied to said transmitter domain;
- a register operating responsive to said first clock signal for registering a system reset signal;
- a clearable register having its data input coupled to an OR logic gate and its clear terminal coupled to an output from said register for registering said system reset signal, wherein a first input of said OR logic gate is driven by an output from said register for detecting said edge in said GFC signal and a second input of said OR logic gate is coupled to said clearable register's data output in a feedback loop path, said clearable register operating to manufacture a common alignment signal that is derived at least in part from said GFC signal;
- a master register operating responsive to said first clock signal for generating a master register output signal by registering said common alignment signal;
- a slave register operating responsive to said first clock signal for generating a slave register output signal by registering said master register output signal;
- a first 2:1 multiplexer (MUX) element coupled to said master and slave registers such that its logic low input is driven by said master register output signal and its logic high input is driven by said slave register output signal, wherein said common alignment signal operates to control said 2:1 MUX element for generating a MUX selection control signal;
- a second 2:1 MUX element operating responsive to said MUX selection control signal for generating a second clock signal dependent on said first clock signal;
- and
- a third 2:1 MUX element operating responsive to said MUX selection control signal for generating said second clock signal's complement.
Dependencies are inferred from the claim text.