Apparatus and method for compression of the timing trace stream

An apparatus for generating a timing trace stream in target processor, a logic signal being associated with each target processor clock cycle, the apparatus comprising:

• a logic unit responsive to a preselected number of logic signals, the logic unit providing a first control signal when all of the preselected logic signals are different, the logic unit providing a second control signal when all of the preselected logic signals are the same;
• a first storage unit responsive to the preselected logic signals for storing the each logic signal in a predetermined storage location, the first storage unit responsive to the first control signal for transferring the contents of the first storage unit;
• and
• a second storage unit responsive to preselected logic signals for storing the current logic signal in a preestablished storage unit location, the second storage unit storing a signal group representing a multiple of the preselected number, the second storage unit responsive to the second logic signal for transferring the contents of the second storage unit.