Method and apparatus for long code generation in synchronous, multi-chip rate systems
OwnerKevin Michael Laird, Jiangnan Chen +1inventors
InventorsKevin Michael Laird, Jiangnan Chen, Frank Fei Zhou
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Abstract
A method and apparatus for long code generation in synchronous, multi-chip rate systems, wherein a first code sequence having a first bit rate, and a second code sequence having the first bit rate, the second code sequence being a time delay of the first code sequence, are multiplexed together, producing a desired long code.
Claims13
A method for code generation in synchronous, multi-chip rate communication systems, comprising the steps of:
- producing a first code sequence having a first bit rate;
- producing a second code sequence having the first bit rate, the second code sequence being a time delay of the first code sequence;
- and
- multiplexing the first code sequence and the second code sequence and producing an output code sequence having a desired bit rate.
A method for long code generation in synchronous, multi-chip rate communication systems, comprising the steps of:
- producing a first long code sequence having a first bit rate;
- producing a second long code sequence having the first bit rate, the second long code sequence being a time delay of the first code sequence;
- producing a third long code sequence having the first bit rate, the third long code sequence being a time delay of the first long code sequence;
- and
- multiplexing the first long code sequence, the second long code sequence, and the third long code sequence, and producing an output code sequence having a desired bit rate.
An apparatus for code generation in synchronous, multichip rate systems, comprising:
- a code generator adapted to produce a first code sequence having a first bit rate;
- an encoder coupled to the code generator and adapted to receive the first code sequence, the encoder adapted to produce a second code sequence having the first bit rate, and
- a multiplexor coupled to the encoder, the multiplexer adapted to receive the first code sequence and the second code sequence, the multiplexor further adapted to produce an output code sequence having a desired bit rate.
An apparatus for long code generation in synchronous, multi-chip rate communication systems, comprising:
- a long code generator adapted to produce a first long code sequence having a first bit rate;
- a convolutional encoder coupled to the long code generator and adapted to receive the first long code sequence, the convolutional encoder adapted to produce a second long code sequence having the first bit rate, the convolutional encoder further adapted to produce a third long code sequence having the first bit rate;
- and
- a multiplexor coupled to the convolutional encoder, the multiplexor adapted to receive the first long code sequence, the second long code sequence, and the third long code sequence, the multiplexor further adapted to produce an output long code sequence having a desired bit rate.
Dependencies are inferred from the claim text.