Semiconductor memory
AssigneeNEC Electronics Corporation
InventorsHiroyuki Takahashi, Hideo Inaba, Atsushi Nakagawa
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Abstract
The present invention provides a non-synchronous semiconductor memory device configured as a pseudo-SRAM and capable of relaxing the limitation to address skew and improving the read rate. A data latch circuit 110 holds data having been read out of memory cells in a memory cell array 106 designated by a tow address included in an address ADD in a read mode. Upon transitions of column addresses A0, A1 included in the address, a multiplexer 111 sequentially and non-synchronously feeds out the data held in the data latch circuit 110 based on the column addresses A0, A1.
Claims7
A semiconductor memory device configured to read out data from a memory cell connected to a bit line by triggering a transition of an address externally supplied, said semiconductor memory device including:
- a hold circuit for reading out and holding, in a read mode, a plurality of data from memory cells designated by a row address and a part of a column address included in said address;
- and
- an input output control circuit for sequentially and non-synchronously feeding out said plurality of data held based on remaining addresses other than both said row address and said part of said column address.
Dependencies are inferred from the claim text.