Voltage regulator and data path for a memory device

A method, comprising:

• generating a two-bit signal representative of the relative strength of an n-channel transistor and a p-channel transistor in an output device;
• enabling with a plurality of switches certain output stages in a pre-driver in response to said signal, wherein said pre-driver includes a first data path and a second data path and wherein said pre-driver produces a variable output drive capability, and wherein at least a pair of said certain output stages is enabled in response to said signal, said pair having an output stage connected to said first data path and another output stage connected to said second data path;
• and
• inputting a high and a low data signal to the output device through said pre-driver.

A pre-driver providing variable output drive capability, comprising:

• a first data path having a plurality of pre-driver output transistors;
• a second data path having a plurality of pre-driver output transistors;
• and
• a plurality of switches, each switch for enabling a pair of said plurality of pre-driver output transistors in response to signals indicative of the strength of driver output transistors in an output device, wherein one of said pair of pre-driver output transistors is connected to said first data path and another of said pair of pre-driver output transistors is connected to said second data path.

A portion of a data path, comprising:

• an output driver responsive to a data signal;
• and
• a pre-driver providing variable output drive capability, comprising:
• a first pre-driver data path having a plurality of output transistors;
• a second pre-driver data path having a plurality of output transistors;
• and
• a plurality of switches, each switch for enabling a pair of said plurality of pre-driver output transistors in response to signals indicative of the strength of output transistors in said output driver, wherein one of said pair of output transistors is connected to said first pre-driver data path and another of said pair of output transistors is connected to said second pre-driver data path, said pre-driver for providing said data signal to said output driver.

A memory device, comprising:

• a plurality of memory cells arranged in an array of rows and columns;
• a plurality of devices for identifying cells within said array;
• a plurality of pads;
• a data path connecting said plurality of pads and said array, said data path including
• an output driver responsive to a data signal;
• and
• a pre-driver providing variable output drive capability, comprising:
• a first pre-driver data path having a plurality of output transistors;
• a second pre-driver data path having a plurality of output transistors;
• and
• a plurality of switches, each switch for enabling a pair of said plurality of pre-driver output transistors in response to signals indicative of the strength of output transistors in said output driver, wherein one of said pair of output transistors is connected to said first pre-driver data path and another of said pair of output transistors is connected to said second pre-driver data path, said pre-driver for providing said data signal to said output driver.

A computer system, comprising:

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus;
• an output device coupled to the processor through the processor bus;
• a memory device coupled to the processor bus, the memory device comprising:
• a plurality of memory cells arranged in an array of rows and columns;
• a plurality of devices for identifying cells within said array;
• a plurality of pads;
• a data path connecting said plurality of pads and said array, said data path including:
• an output driver responsive to a data signal;
• and
• a pre-driver providing variable output drive capability, comprising:
• a first pre-driver data path having a plurality of pre-driver output transistors;
• a second pre-driver data path having a plurality of pre-driver output transistors;
• and
• a plurality of switches, each switch for enabling a pair of said plurality of pre-driver output transistors in response to signals indicative of the strength of output transistors in said output driver, wherein one of said pair of pre-driver output transistors is connected to said first pre-driver data path and another of said pair of output transistors is connected to said second pre-driver data path, said pre-driver for providing said data signal to said output driver.