Method and apparatus for lengthening the data-retention time of a dram device in standby mode

A method of operating a memory system having an array of memory cells that require periodic refresh, the method comprising:

• operating the array of memory cells in a single-cell mode during normal operating conditions;
• entering a standby mode from the normal operating conditions;
• and
• selecting the standby mode from a plurality of possible standby modes.

A method of operating a memory system having a plurality of memory blocks that require periodic refresh, the method comprising:

• operating the memory blocks in a single-cell mode during normal operating conditions;
• entering a standby mode from the normal operating conditions;
• and
• selecting the a first standby mode for a first set of one or more memory blocks of the plurality of memory blocks;
• and
• selecting a second standby mode for a second set of one or more memory blocks of the plurality of memory blocks, the first standby mode being different than the second standby mode.

A refresh controller for controlling refresh operations in an array of memory cells that require refresh operations to retain data, the refresh controller comprising:

• a refresh timer configured to generate a first refresh enable signal having a first period, and a second refresh enable signal having a second period, wherein the second period is longer than the first period;
• first control circuitry configured to assert a first control signal to indicate that a differential-cell standby mode is being entered;
• decoder circuitry configured to convert data stored in the array of memory cells from a single-cell mode to a differential-cell mode when the first control signal is asserted;
• second control circuitry configured to assert a second control signal to indicate that the data stored in the array of memory cells has been converted from a single-cell mode to a differential-cell mode;
• a selection circuit configured to use the first refresh enable signal to control refresh operations when data is stored in the array of memory cells in the single-cell mode, and configured to use the second refresh enable signal to control refresh operations when data is stored in the array of memory cells in the differential-cell mode, wherein the selection circuit is controlled by the second control signal.