Apparatus and method for testing redundant memory elements

A semiconductor device, comprising:

• a primary memory array comprising primary columns and primary rows, the primary memory array operable to store data;
• a primary addressing circuit operable to select the primary columns and primary rows;
• a redundant memory array comprising redundant columns and redundant rows, the redundant memory array operable to store data and operable to be programmed from a programmable state to provide the redundant columns and redundant rows for defective primary columns and primary rows;
• a column signal pad operable to receive column serial selection data;
• a row signal pad operable to receive row serial selection data;
• and
• a redundant addressing circuit connected to the column and row signal pads and operable to select the redundant columns and redundant rows, and further operable to receive the column serial selection data from the column signal pad and to select a corresponding redundant column in response, and to receive the row serial selection data from the row signal pad and to select a corresponding redundant row in response.

A semiconductor device, comprising:

• primary memory means for storing data;
• redundant memory means for storing data and for providing redundant memory elements for defective primary memory means;
• input means for providing serial test data for the redundant memory means;
• primary addressing means for addressing the primary memory means and for disabling accessing of the primary memory means when the input means provides the serial test data;
• and
• redundant addressing means for addressing the redundant memory means and for receiving the serial test data for accessing the redundant memory means.

A method of testing redundant memory elements in a semiconductor device, the redundant memory elements selectable by a redundant addressing device, the method comprising the steps of:

• receiving serial selection data through a first test pad on the semiconductor device;
• accessing a corresponding redundant memory element in response to the serial selection data received;
• and
• disabling the selection of primary memory elements.

A method of testing redundant memory elements in a semiconductor device, the redundant memory elements selectable by a redundant addressing device, the method comprising the steps of:

• generating serial selection data corresponding to the selection of redundant memory elements in the semiconductor device;
• providing the serial selection data to a first test pad on the semiconductor device;
• conducting a memory test of the redundant memory elements corresponding to the serial selection data provided;
• determining whether the redundant memory elements under test pass the memory test;
• and
• storing address data of redundant memory elements that fail the memory test.

Semiconductor device test circuitry for testing redundant memory elements in the semiconductor device, the redundant memory elements selectable by a redundant addressing device, comprising:

• means for receiving serial selection data;
• means for accessing a corresponding redundant memory element in response to the serial selection data received;
• and
• means for disabling a selection of primary memory elements in the semiconductor device when the serial selection data is received by the means for accessing a corresponding redundant memory element.

A system for testing redundant memory elements in a semiconductor device, the redundant memory elements selectable by a redundant addressing device, the system comprising:

• means for generating serial selection data corresponding to the selection of redundant memory elements in the semiconductor device;
• means for providing the serial selection data to a first test pad on the semiconductor device;
• means for conducting a memory test of the redundant memory elements corresponding to the serial selection data provided;
• means for determining whether the redundant memory elements under test pass the memory test;
• and
• means for storing address data of redundant memory elements that fail the memory test.