Variable impedence output buffer

An output buffer for a flash memory device, comprising:

• a pull-up driver coupled between a power supply node and an output node;
• a pull-down driver coupled between a ground node and the output node;
• a pull-up pre-driver coupled to the pull-up driver;
• and
• a pull-down pre-driver coupled to the pull-down driver;
• wherein the pull-up and pull-down drivers each comprise a plurality of cascode-connected drive transistors;
• and
• wherein a gate of at least one of the cascode-connected drive transistors in each driver is coupled to the output node.

An output buffer for a semiconductor memory device, comprising:

• a pull-down output driver stage, comprising:
• a first NMOS pull-down transistor coupled between a ground node and an output pad, and
• second and third NMOS pull-down transistors coupled in cascode between the ground node and the output pad, the second NMOS pull-down transistor comprising a gate coupled to a gate of the first NMOS pull-down transistor;
• a pull-up output driver stage, comprising:
• a first PMOS pull-up transistor coupled between a power supply node and the output pad, and
• second and third PMOS pull-up transistors coupled in cascode between the power supply node and the output pad, the second PMOS pull-up transistor comprising a gate coupled to a gate of the first PMOS pull-up transistor and the third PMOS pull-up transistor comprising a gate coupled to a gate of the third NMOS pull-down transistor;
• a pull-up pre-driver stage coupled to the gate of the second PMOS pull-up transistor;
• and
• a pull-down pre-driver stage coupled to the gate of the second NMOS pull-down transistor.

A flash memory device, comprising:

• a non-volatile memory array;
• an output buffer coupled to the memory array;
• and
• at least one programmable interconnect to selectively configure the output buffer for operation at a predetermined supply voltage range.

A flash memory device, comprising:

• an array of non-volatile memory cells;
• and
• an output buffer coupled to the array, wherein the output buffer further comprises:
• an output pad for providing a signal representative of a data value of a memory cell of the array;
• a pull-down output driver stage, comprising:
• a first NMOS pull-down transistor coupled between a ground node and the output pad, and
• second and third NMOS pull-down transistors coupled in cascode between the ground node and the output pad, the second NMOS pull-down transistor comprising a gate coupled to a gate of the first NMOS pull-down transistor;
• and
• a pull-up output driver stage, comprising:
• a first PMOS pull-up transistor coupled between a power supply node and the output pad, and
• second and third PMOS pull-up transistors coupled in cascode between the power supply node and the output pad, the second PMOS pull-up transistor comprising a gate coupled to a gate of the first PMOS pull-up transistor and the third PMOS pull-up transistor comprising a gate coupled to a gate of the third NMOS pull-down transistor.

A method for providing an impedance-adaptive output buffer for use in a flash memory device, comprising:

• coupling a pull-up driver between a power supply node and an output node and
• coupling a pull-down driver between a ground node and the output node;
• coupling a pull-up pre-driver to the pull-up driver, and
• coupling a pull-down pre-driver to the pull-down driver,
• wherein the pull-up and pull-down drivers comprise cascode-connected output transistors.

An output buffer, comprising:

• a pull-up driver stage coupled to receive a first signal for coupling an output node of the output buffer to a supply potential node in response to the first signal having a first logic level and for presenting a high impedance to the output node in response to the first signal having a second logic level;
• and
• a pull-down driver stage coupled to receive a second signal for coupling the output node to a ground potential node in response to the second signal having the second logic level and for presenting a high impedance to the output node in response to the second signal having a first logic level;
• wherein the pull-up driver stage comprises at least two cascode-connected transistors coupled between the supply potential node and the output node with at least one of its cascode-connected transistors coupled to receive the first signal on its gate and at least one of its cascode-connected transistors having its gate coupled to the output node;
• and
• wherein the pull-down driver stage comprises at least two cascode-connected transistors coupled between the ground potential node and the output node with at least one of its cascode-connected transistors coupled to receive the second signal on its gate and at least one of its cascode-connected transistors having its gate coupled to the output node.

An electronic system, comprising:

• an array of non-volatile memory cells;
• a processor;
• and
• an input/output (I/O) circuit for providing bi-directional communications between the processor and the array of non-volatile memory cells;
• wherein the I/O circuit includes an output buffer having an output node, the output buffer comprising:
• a pull-up pre-driver section coupled to receive a first signal indicative of a data value of a memory cell of the array;
• a pull-down pre-driver section coupled to receive a second signal indicative of the data value of the memory cell of the array, wherein the first signal and the second signal are generally of the same logic level;
• a pull-up driver stage coupled to receive an output signal from the pull-up pre-driver section for coupling the output node to a supply potential node in response to the first signal having a first logic level and for presenting a high impedance to the output node in response to the first signal having a second logic level;
• and
• a pull-down driver stage coupled to receive an output signal from the pull-down pre-driver section for coupling the output node to a ground potential node in response to the second signal having the second logic level and for presenting a high impedance to the output node in response to the second signal having a first logic level;
• wherein each driver stage comprises feedback circuitry to dynamically control an impedance of the output buffer in response to a load condition between the output buffer and the processor.

A method of fabricating an output buffer for a semiconductor device, comprising:

• selecting between operation at a first supply potential or a second supply potential, wherein the second supply potential is higher than the first supply potential;
• fabricating transistors of driver and pre-driver sections of the output buffer to have a first thickness for the first supply potential or a second thickness for the second supply potential, wherein the second thickness is higher than the first thickness;
• fabricating the transistors to have a first doping level for the first supply potential or a second doping level for the second supply potential, wherein the second doping level is lower than the first doping level;
• fabricating the transistors to have a first gate length for the first supply potential or a second gate length for the second supply potential, wherein the second gate length is longer than the first gate length and wherein a space to accommodate the second gate length is provided whether the first gate length or the second gate length is chosen;
• and
• fabricating a pull-down stage of a level shifter of the output buffer to have a first size for the first supply potential and a second size for the second supply potential, wherein the first size is smaller than the second size, and wherein the size of the pull-down stage is determined by programming of one or more programmable interconnects to selectively engage or disengage circuit elements of the level shifter.