Non-volatile semiconductor memory device in which one page is set for a plurality of memory cell arrays

A non-volatile semiconductor memory device comprising:

• a plurality of memory cell arrays each having a plurality of memory cells, said plurality of memory cells being connected to a plurality of word lines;
• a plurality of word line drive circuits which are connected to said plurality of memory cell arrays, and which select and drive said plurality of word lines of the corresponding memory cell arrays;
• and
• a plurality of control circuits which are connected to said plurality of memory cell arrays, and which have a plurality of latch circuits which latch write data to be written to said plurality of memory cells of the corresponding memory cell arrays and execute verifying reading of data which has been written in said plurality of memory cells, thereby latching read data, and at a time of data writing, controls a select and drive operation for said word lines in the corresponding word line drive circuit in accordance with write data latched by said plurality of latch circuits, and at a time of verifying reading, controls a select and drive operation for said word lines in the corresponding word line drive circuit in accordance with verifying read data latched by said plurality of latch circuits.

A non-volatile semiconductor memory device comprising:

• a plurality of memory cell arrays each having a plurality of memory cells, said plurality of memory cells being connected to a plurality of word lines;
• a plurality of word line drive circuits which are connected to said plurality of memory cell arrays, and which select and drive said plurality of word lines of the corresponding memory cell arrays;
• and
• a plurality of control circuits which are connected to said plurality of memory cell arrays, and which have a plurality of latch circuits which latch write data to be written to said plurality of memory cells of the corresponding memory cell arrays, and at a time of data writing, controls a select and drive operation for said word lines in the corresponding word line drive circuit in accordance with write data latched by said plurality of latch circuits, wherein when all of said write data latched by said plurality of latch circuits are logic data which do not require the write operation to said memory cells, the corresponding word line drive circuit is controlled by said control circuit such that the select and drive operation for said word lines of the corresponding memory cell is not initiated.