Erasing method for non-volatile memory
AssigneeMacronix International Co., Ltd.
InventorsWen-Jer Tsai, Chih-Chieh Yeh, Tao-Cheng Lu, Samuel C. Pan
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Abstract
An erasing method for the memory cells of a non-volatile memory is provided. Each memory cell comprises a gate, a source, a drain, an electron-trapping layer and a substrate. The data within the memory cell is erased by applying a first voltage to the control gate, applying a second voltage to the source, applying a third voltage to the drain and applying a fourth voltage to the substrate. The electrons are pulled from the electron-trapping layer into the channel by negative gate F-N tunneling effect.
Claims26
An erasing method for non-volatile memory, wherein the non-volatile memory has a gate, a source, a drain, an electron-trapping layer and a substrate, the erasing method comprising the steps of:
- applying a first voltage to the gate, applying a second voltage to the source, applying a third voltage to the drain and applying a fourth voltage to the substrate so that electrons are pulled out from the electron-trapping layer into the channel of a memory cell utilizing a negative gate F-N tunneling effect in an erasing operation.
An operating method for a non-volatile memory, wherein the non-volatile memory includes a gate, a source, a drain, an electron-trapping layer and a substrate, the operating method comprising the steps of:
- programming the non-volatile memory to a programmed threshold voltage VtP;
- and
- setting the non-volatile memory to an erased threshold voltage VtE by applying a first voltage to the gate, applying a second voltage to the drain, applying a third voltage to the source and applying a fourth voltage to the substrate so that electrons are pulled out from the electron-trapping layer into the channel of a memory cell utilizing a negative gate F-N tunneling effect in an erasing operation.
Dependencies are inferred from the claim text.