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US 2004/0170056 A1Published application
Semiconductor memory device for storing multivalued data
AssigneeKabushiki Kaisha Toshiba
InventorsNoboru Shibata, Tomoharu Tanaka
Life of this patent
Estimating the term…
Abstract
Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction.
Claims20
A semiconductor memory device comprising:
- a memory cell array configured by arranging a plurality of memory cells in a matrix, each of which is capable of having at least one of four threshold voltages and storing two bits of data;
- a plurality of bit lines connected to said plurality of memory cells arranged in the column direction;
- a plurality of word lines connected to said plurality of memory cells arranged in the row direction;
- a flag cell which is selected at the same time when the memory cells are selected by each of the word lines;
- a plurality of data storage circuits which are connected to said plurality of bit lines in a one-to-one correspondence and store data;
- a write circuit which writes data on a first page into a plurality of first memory cells selected simultaneously by one of the word lines, then writes data on a second page into said plurality of first memory cells and, when the data on the second page is written, writes data into the flag cell simultaneously selected by the word line, and thereafter writes the data on the first and second pages sequentially into a second memory cell adjacent to the first memory cells in the bit line direction.
3 more elements
A semiconductor memory device comprising:
- a memory cell array configured by arranging a plurality of memory cells in a matrix, each of which is capable of having at least one of four threshold voltages and storing two bits of data;
- a plurality of bit lines connected to said plurality of memory cells arranged in the column direction;
- a plurality of word lines connected to said plurality of memory cells arranged in the row direction;
- a plurality of data storage circuits which are connected to said plurality of bit lines in a one-to-one correspondence and store data;
- a write circuit which writes data on a first page into a first and a second memory cell adjoining in the bit line, then writes data on a second page into the first memory cell, and thereafter writes the data on the first page into a third memory cell adjacent to the second memory cells in the bit line direction.
2 more elements
A semiconductor memory device comprising:
- a memory cell array configured by arranging a plurality of memory cells in a matrix, each of which is capable of having one of an 2n (n is a natural number equal to 2 or more) number of threshold voltages and storing an n number of bits of data;
- a plurality of bit lines connected to said plurality of memory cells arranged in the column direction;
- a plurality of word lines connected to said plurality of memory cells arranged in the row direction;
- a first and a second flag cell which are selected at the same time when the memory cells are selected by the word lines;
- a write circuit which divides an n number of pages composed of an n number of bits stored in a plurality of memory cells selected by one of the word lines into a first and a second area and, when writing data into the first area on a k-th page (2<=k<=n), writes the data into also the first flag cell and, when writing data into the second area on the k-th page, writes the data into also the second flag cell.
2 more elements
A semiconductor memory device comprising:
- a memory cell array configured by arranging a plurality of memory cells in a matrix, each of which is capable of having one of an 2n (n is a natural number equal to 2 or more) number of threshold voltages and storing an n number of bits of data;
- a plurality of bit lines connected to said plurality of memory cells arranged in the column direction;
- a plurality of word lines connected to said plurality of memory cells arranged in the row direction;
- an (n−1)×i number of flag cells which are selected at the same time when the memory cells are selected by the word lines;
- a write circuit which divides an n number of pages composed of an n number of bits stored in a plurality of memory cells selected by one of the word lines into an i number (i is a natural number) of areas and, when writing data into the first area on a k-th page (2<=k<=n), writes the data into also the ((k−2)×i+1)-th flag cell and, when writing data into the i-th area on the k-th page, writes the data into also the (k−1)×i)-th flag cell.
2 more elements
A semiconductor memory device comprising:
- a memory cell array configured by arranging a plurality of memory cells in a matrix, each of which is capable of having one of an 2n (n is a natural number equal to 2 or more) number of threshold voltages and storing an n number of bits of data;
- a plurality of bit lines connected to said plurality of memory cells arranged in the column direction;
- a plurality of word lines connected to said plurality of memory cells arranged in the row direction;
- an i number of flag cells which are selected at the same time when the memory cells are selected by the word lines;
- a write circuit which divides an n number of pages composed of an n number of bits stored in a plurality of memory cells selected by one of the word lines into an i number (i is a natural number) of areas and, when writing data into the first area on a k-th page (2<=k<=n), writes the data into also the first flag cell and, when writing data into the i-th area on the k-th page, writes the data into also the i-th flag cell.
2 more elements
A semiconductor memory device comprising:
- a memory cell array configured by arranging a plurality of memory cells in a matrix, each of which is capable of having one of four threshold voltages and storing two bits of data;
- a plurality of bit lines, each of which is connected to said plurality of memory cells arranged in the column direction;
- a plurality of word lines, each of which is connected to said plurality of memory cells arranged in the row direction;
- a first flag cell and a second flag cell which are selected at the same time when the memory cells are selected by each of the word lines;
- and
- a control section which, when writing the data in a second page composed of the two bits into the memory cells selected by the word line, writes specific data into the first and second flag cells and which, when reading the data in a first page from the memory cells, determines from the data read from the first flag cell whether the second page has been written into the memory cells and which, when reading the data in the second page from the memory cells, determines from the data read from the second flag cell whether the second page has been written into the memory cells.
3 more elements
A semiconductor memory device comprising:
- a memory cell array configured by arranging a plurality of memory cells in a matrix, each of which is capable of having one of a 2n (n is a natural number equal to 2 or more) number of threshold voltages and storing an n number of bits of data;
- a plurality of bit lines, each of which is connected to said plurality of memory cells arranged in the column direction;
- a plurality of word lines, each of which is connected to said plurality of memory cells arranged in the row direction;
- an n number of flag cells which are selected at the same time when the memory cells are selected by each of the word lines;
- and
- a control section which, when writing the data in a k-th page (2<=k<=n) composed of a k number of bits into the memory cells selected by the word line, writes specific data into a k number (2<=k<=n) of the flag cells and which, when reading the data in an i-th page (i<=n) from the memory cells, determines from the data read from the i-th flag cell whether the k-th page has been written into the memory cells.
3 more elements
A semiconductor memory device comprising:
- a memory cell array configured by arranging a plurality of memory cells in a matrix, each of which is capable of having one of a 2n (n is a natural number equal to 2 or more) number of threshold voltages and storing an n number of bits of data;
- a plurality of bit lines, each of which is connected to said plurality of memory cells arranged in the column direction;
- a plurality of word lines, each of which is connected to said plurality of memory cells arranged in the row direction;
- an (n+(n−1)+(n−2) . . . 2) number of flag cells which are selected at the same time when the memory cells are selected by each of the word lines;
- and
- a control section which, when writing the data in a k-th page (2<=k<=n) composed of a k number of bits into the memory cells selected by the word line, writes specific data into a k number (2<=k<=n) of the flag cells and which, when reading the data in an i-th page (i<=n) from the memory cells, determines from the data read from the i-th flag cell whether the k-th page has been written into the memory cells.
3 more elements
Dependencies are inferred from the claim text.