Phase change memory array
AssigneeSamsung Electronics Co., Ltd.
InventorsKeun-ho Lee, Chang-sub Lee
Life of this patent
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Abstract
A phase change memory includes a plurality of word lines, a plurality of bits lines intersecting the word lines, and a plurality of memory cells arranged in rows along the word lines and located at corresponding intersection regions of the word lines and bit lines. Each of the memory cells includes a cell transistor having a gate connected to a corresponding word line, and a resistor and a phase change cell connected in series between a drain of the cell transistor and a corresponding bit line. In order to increase a cell drive current, the phase change memory also includes a plurality of auxiliary transistors respectively connected between the drains of the cell transistors of adjacent said memory cells.
Claims27
A phase change memory cell array, comprising:
- a plurality of word lines;
- a plurality of bit lines intersecting the word lines;
- a plurality of memory cells arranged in rows along the word lines and located at corresponding intersection regions of the word lines and bit lines, respectively, wherein each of the memory cells includes (a) a cell transistor having a gate connected to a corresponding word line, and (b) a resistor and a phase change cell connected in series between a drain of the cell transistor and a corresponding bit line;
- and
- a plurality of auxiliary transistors respectively connected between the drains of the cell transistors of adjacent said memory cells.
A phase change memory array, comprising:
- a plurality of word lines;
- a plurality of bit lines intersecting the word lines;
- a plurality of memory cells arranged in rows along the word lines and located at corresponding intersection regions of the word lines and bit lines, respectively, wherein each of the memory cells includes (a) a cell transistor having a gate connected to a corresponding word line, and (b) a resistor and a phase change cell connected in series between a drain of the cell transistor and a corresponding bit line;
- and
- a plurality of vertical gates respectively interposed between the drains of the cell transistors of adjacent said memory cells, wherein each of the vertical gates extends from and in a same layer as a corresponding word line.
A phase change memory array, comprising:
- a plurality of word line pairs;
- a plurality of bit lines intersecting the word line pairs;
- a plurality of memory cells arranged in rows between the word lines of a corresponding word line pair and located at intersection regions of the word line pairs and bit lines, respectively, wherein each of the memory cells includes (a) a cell transistor having a gate connected to a corresponding word line pair, and (b) a resistor and a phase change cell connected in series between a drain of the cell transistor and a corresponding bit line;
- and
- a plurality of vertical gates respectively interposed between the drains of the cell transistors of adjacent said memory cells, wherein each of the vertical gates is connected between the word lines of a corresponding word line pair and in a same layer as the corresponding word line pair.
A phase change memory array, comprising:
- a plurality of word line pairs;
- a plurality of bit lines intersecting the word line pairs;
- a plurality of memory cells arranged in rows between the word lines of a corresponding word line pair and located at intersection regions of the word line pairs and bit lines, respectively, wherein each of the memory cells includes (a) a cell transistor having a gate connected to a corresponding word line pair, and (b) a resistor and a phase change cell connected in series between a drain of the cell transistor and a corresponding bit line;
- and
- a plurality of vertical gates respectively connected at one end between the word lines of a respective word line pair and in a same layer as the respective word line pair.
Dependencies are inferred from the claim text.