Semiconductor integrated circuit device with improved storage MOSFET arrangement

A semiconductor integrated circuit device comprising:

• a plurality of memory cells, each having a storage MOSFET holding an information in a gate of the storage MOSFET and a write transistor supplying a write information voltage corresponding to the information to the gate of the storage MOSFET;
• and
• a plurality of word lines coupled with the plurality of memory cells,
• wherein the write information voltage is selected from a first voltage and a second voltage greater than the first voltage corresponding to the information to be stored in the memory cell and is supplied to the gate of the storage MOSFET,
• wherein, in a write operation of the semiconductor integrated circuit device, the storage MOSFET is set to an OFF state regardless of the write information voltage,
• wherein, in a read operation of the semiconductor integrated device, the write information voltage is boosted by a transition of a voltage of the word lines,
• wherein, when the write information voltage is the first voltage, the storage MOSFET is set to the OFF state in the read operation, and
• wherein, when the write information voltage is the second voltage, the storage MOSFET is set to an ON state in the read operation.

A semiconductor integrated circuit device comprising:

• a memory array, wherein the memory array further includes;
• a plurality of memory cells, each having a storage MOSFET holding an information voltage in a gate of the storage MOSFET and set to an ON or OFF state according to the information voltage, and a write transistor supplying a write information voltage corresponding to the information voltage to the gate of the storage MOSFET;
• a plurality of write data lines, each being applied with the write information voltages given as the information voltage of corresponding ones of the memory cells;
• a plurality of read data lines, each being applied with a read information corresponding to the ON or OFF state of the storage MOSFET of the memory cells;
• a word line structure connected to the plurality of memory cells;
• a data line select circuit selecting one of the plurality of read data lines;
• and
• first and second common data lines being connected to one of the read data lines selected by the data line select circuit,
• wherein, during a non-select state, the write transistor is set to an OFF state and the storage MOSFET is set to on OFF state,
• wherein, in a first select period, the write transistor is set to an OFF state, the read data line is discharged when the information voltage is high level or the read data line is not discharged when the information voltage is low level,
• wherein, in a second select period, in which either the information voltage to be written into the write data lines or a read information voltage corresponding to the read information are applied, the write transistor is set to ON state,
• wherein the first and second common data lines are precharged to a precharge voltage that is a voltage between a high level voltage and a low level voltage at a time of amplifying voltages on the first and the second common data lines in the non-select state, and
• wherein the read information which appears on one of the first and second common data lines corresponding to a voltage which appeared on the read data line selected by the data line select circuit is amplified using the precharge voltage of the other of the first and second common data lines as a reference voltage.