US 2004/0170044 A1 · Semiconductor integrated circuit device

Abstract

There is provided a semiconductor integrated circuit device which has realized high speed operation, high integration density and highly efficient layout of the RAM macro, in which a memory array which is divided into four sections in the X and Y coordinates directions is disposed, a first input circuit for receiving a signal which requires optimization for a signal delay is disposed to the center of such four memory arrays, a second input circuit for receiving a data input and control signals thereof is disposed to the center of Y coordinate corresponding to the extending direction of the word line and a signal line for transferring an input signal from the external circuit of the RAM macro to the first and second input circuits is formed using an upper layer wiring for the wiring to form the memory array.

Claims26

Dependent claims

A semiconductor integrated circuit device comprising a RAM macro, including:

memory arrays divided into four memory arrays in the X and Y coordinates directions;
a first input circuit provided at the center of said four memory arrays for receiving a first signal;
and
a second input circuit provided between two memory arrays which are disposed side by side in the direction of said Y coordinate among four memory arrays for receiving a second signal,
wherein a signal line for transferring said first and second signals to said first and second input circuits from the external side of said RAM macro is formed using an upper layer wiring for the wiring to form said memory array, and
wherein said upper layer wiring is formed in the area to form a system wiring for connecting macros.

3 more elements

A semiconductor integrated circuit device, comprising a RAM macro, including:

a first region, a second region and a third region which are respectively formed in the square shape and are disposed continuously in this sequence in the first direction;
a fourth region, a fifth region and a sixth region which are respectively formed in the square shape and are disposed continuously in this sequence in said first direction;
and
a seventh region, an eighth region and a ninth region which are respectively formed in the square shape and are disposed continuously in this sequence in said first direction,
wherein said first, fourth and seventh regions are continuously disposed in this sequence in the second direction which is perpendicular to said first direction,
wherein said second, fifth and eighth regions are continuously disposed in this sequence in said second direction,
wherein said third, sixth and ninth regions are continuously disposed in this sequence in said second direction,
wherein a first memory array including a plurality of first memory cells is formed to said first region,
wherein a second memory array including a plurality of second memory cells is formed to said third region,
wherein a third memory array including a plurality of third memory cells is formed to said seventh region,
wherein a fourth memory array including a plurality of fourth memory cells is formed to said ninth region, and
wherein an input terminal of said RAM macro is disposed to at least one region among said fourth, fifth and sixth regions.

9 more elements

A semiconductor integrated circuit device, including:

a first region, a second region and a third region which are respectively formed in the square shape and continuously disposed in the first direction;
a fourth region, a fifth region and a six region which are respectively formed in the square shape and continuously disposed in said first direction;
and
a seventh region, an eighth region and a ninth region which are respectively formed in the square shape and continuously disposed in said first direction;
wherein said first, fourth and seventh regions are continuously disposed in this sequence in the second direction which is perpendicular to said first direction,
wherein said second, fifth and eighth regions are disposed continuously in this sequence in said second direction,
wherein said third, sixth and ninth regions are disposed continuously in this sequence in said second direction,
wherein a first memory array including a plurality of first memory cells is formed in said first region,
wherein a second memory array including a plurality of second memory cells is formed in said third region,
wherein a third memory array including a plurality of third memory cells is formed in said seventh region,
wherein a fourth memory array including a plurality of fourth memory cells is formed in said ninth region,
wherein each of said second, fourth, fifth, sixth and eighth regions is smaller than each of said first, third, seventh and ninth regions, and
wherein at least a part of the address input circuit is formed in said fifth region.

10 more elements

A semiconductor integrated circuit device, including:

a first region, a second region and a third region which are formed in the square shape and disposed continuously in the first direction;
a fourth region, a fifth region and a sixth region which are formed in the square shape and disposed continuously in said first direction;
and
a seventh region, an eighth region and a ninth region which are formed in the square shape and disposed continuously in said first direction,
wherein said first, fourth and seventh regions are continuously disposed in this sequence in the second direction which is perpendicular to said first direction,
wherein said second, fifth and eighth regions are continuously disposed in this sequence in said second direction,
wherein said third, sixth and ninth regions are continuously disposed in this sequence in said second direction,
wherein a first memory array including a plurality of first memory cells is formed in said first region,
wherein a second memory array including a plurality of second memory cells is formed in said third region,
wherein a third memory array including a plurality of third memory cells is formed in said seventh region,
wherein a fourth memory array including a plurality of fourth memory cells is formed in said ninth region,
wherein each of said second, fourth, fifth, sixth and eighth regions is smaller than each of said first, third, seventh and ninth regions, and
wherein at least a part of the clock input circuit is formed in said fifth region.

10 more elements

Dependencies are inferred from the claim text.

Semiconductor integrated circuit device

Life of this patent

Semiconductor integrated circuit device

Life of this patent

Abstract

Claims26