Interlayered power bus for semiconductor device
AssigneeUnion Semiconductor Technology Corporation
InventorWayne Arthur Theel
Life of this patent
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Abstract
A semiconductor device includes a first power pad, a second power pad, a first adjacent bus pair, and a second adjacent bus pair. The first power pad is operable to supply a first potential, and the second power pad operable to supply a second potential. The first adjacent bus pair is disposed on a first layer of the semiconductor device and connected to the first and second power pad. The second adjacent bus pair is disposed on the second layer of the semiconductor device and is connected to the first and second power pads, and is also underlying the first adjacent bus pair.
Claims55
A semiconductor device, comprising:
- a first power pad operable to supply a first potential;
- a second power pad operable to supply a second potential;
- and
- a first power network comprising first busses and second busses interlayered on first and second layers of the semiconductor device, the first busses connected to the first power pad and the second busses connected to the second power pad.
A method of providing power to an integrated circuit, the method comprising:
- interlayering first busses on first and second layers of the integrated circuit;
- interlayering second busses on the first and second layers of the integrated circuit;
- connecting the first busses to a first potential;
- connecting the second busses to a second potential.
A system for providing power to an integrated circuit, comprising:
- first interlayered bus means for providing first busses on first and second layers of the integrated circuit;
- second interlayered bus means for providing second busses on the first and second layers of the integrated circuit;
- means for connecting the first busses to a first potential;
- and
- means for connecting the second busses to a second potential.
A semiconductor device, comprising:
- a first power pad operable to supply a first potential;
- a second power pad operable to supply a second potential;
- and
- a first adjacent bus pair disposed on a first layer of the semiconductor device, the first adjacent bus pair connected to the first and second power pads;
- and
- a second adjacent bus pair disposed on the second layer of the semiconductor device, the second adjacent bus pair connected to the first and second power pads and underlying the first adjacent bus pair in an elongated direction.
A semiconductor device, comprising:
- a first power pad operable to supply a first potential;
- a second power pad operable to supply a second potential;
- and
- a first power network comprising first busses and second busses interlayered on a plurality of layers of the semiconductor device, the first busses connected to the first power pad and the second busses connected to the second power pad.
Dependencies are inferred from the claim text.