Multi-match detection circuit for use with content-addressable memories
AssigneeMicron Technology, Inc.
InventorZvi Regev
Life of this patent
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Abstract
A method and circuit for detecting multiple match conditions in a content addressable memory is disclosed. The circuit detects the multiple matches using a transistor array which is arranged as logical AND and OR gates. A current sensing detector provides multiple match detection when a current path is established through the transistor array when a multiple match exists.
Claims23
A multiple match detector for use in a content addressable memory, comprising:
- a plurality of input pins, each connected to a match detector of said content addressable memory;
- a plurality of transistors connected to said input pins, logically arranged to detect a multiple match condition;
- a multiple match condition being indicated by an electrical current path to a sensing pin through at least some of said plurality of transistors;
- a current source transistor for sourcing and/or limiting the current through said electrical path;
- and
- a current sense circuit connected to said sensing pin, for outputting a signal when a multiple match condition has been detected.
A multiple match detection circuit for use in a content-addressable memory, comprising:
- a plurality of first multiple match detectors for detecting a multiple match condition within a predetermined set of match lines;
- the inputs of all of said first multiple match detectors being simultaneously connected to a plurality of logic gates, the outputs of said logic gates being connected to an second multiple match detector so as to detect multiple match conditions spanning multiple sets of match lines.
A method for detecting multiple matches in a content addressable memory, comprising:
- monitoring a plurality of match lines;
- arranging a plurality of transistors to achieve logical AND and logical OR functionality;
- sorting the signals present on said match lines using said logical functionality;
- detecting when a plurality of said signals are asserted;
- and
- outputting an signal that said plurality of match signals has occurred.
A processor circuit, comprising
- a processor;
- and
- a content-addressable memory circuit for exchanging data with said processor;
- at least one of said processor and memory circuit comprising a multiple match detection circuit comprising:
- a plurality of input pins, each connected to a match line of said content addressable memory;
- a plurality of transistors connected to said input pins, logically arranged to detect a multiple match condition;
- a multiple match condition being indicated by an electrical current path to a sensing pin through at least some of said plurality of transistors;
- a current source transistor for sourcing and/or limiting the current through said electrical path;
- and
- a current sense circuit connected to said sensing pin, for outputting a signal when a multiple match condition has been detected.
A multiple match detector for use in a content addressable memory, comprising:
- a plurality of input pins, each connected to a match detector of said content addressable memory;
- a plurality of transistors connected to said input pins, logically arranged to detect a multiple match condition;
- a multiple match condition being indicated by an electrical current path to a sensing pin through at least some of said plurality of transistors;
- a current sense circuit connected to said sensing pin, for outputting a signal when a multiple match condition has been detected.
Dependencies are inferred from the claim text.