US 2004/0169548 A1 · Simple step-up apparatus including level shift circuits capable of low breakdown voltage · patentgrep

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Abstract

In a step-up apparatus, a first level shift circuit receives a first clock signal to generate two phase-opposite second clock signals, and a second level shift circuit receives the first clock signal to generate two phase-opposite third clock signals. A charge pump circuit steps up a power supply voltage at a power supply voltage terminal using the second clock signals to generate a positive voltage, and a polarity inverting circuit inverts the positive voltage using the third clock signals to generate a negative voltage whose absolute value is the same as the positive voltage. A high level of the second clock signals is not higher than the positive voltage, and a low level of the second clock signals is not lower than a voltage at a ground terminal. A high level of the third clock signals is not higher than the power supply voltage, and a low level of the third clock signals is not lower than the negative voltage.

Claims46

Dependent claims

A step-up apparatus comprising:

a first level shift circuit for receiving a first clock signal to generate two phase-opposite second clock signals;
a second level shift circuit for receiving said first clock signal to generate two phase-opposite third clock signals;
a charge pump circuit, connected to said first level shift circuit, for stepping up a power supply voltage at a power supply voltage terminal using said second clock signals to generate a positive voltage;
and
a polarity inverting circuit, connected to said charge pump circuit and said second level shift circuit, for inverting said positive voltage using said third clock signals to generate a negative voltage whose absolute value is the same as said positive voltage,
a high level of said second clock signals being not higher than said positive voltage,
a low level of said second clock signals being not lower than a voltage at a ground terminal,
a high level of said third clock signals being not higher than said power supply voltage,
a low level of said third clock signals being not lower than said negative voltage.

6 more elements

A step-up apparatus comprising:

a first level shift circuit for receiving a clock first signal to generate two phase-opposite second clock signals;
a second level shift circuit for receiving said first clock signal to generate a third clock signal;
a charge pump circuit, connected to said first level shift circuit, for stepping up a power supply voltage at a power supply voltage terminal using said second clock signals to generate a positive voltage;
and
a polarity inverting circuit, connected to said charge pump circuit and said second level shift circuit, for inverting said positive voltage using said third clock signal to generate a negative voltage whose absolute value is the same as said positive voltage,
a high level of said second clock signals being not higher than said positive voltage,
a low level of said second clock signals being not lower than a voltage at a ground terminal,
a high level of said third clock signal being not higher than said voltage at said ground voltage,
a low level of said third clock signal being not lower than said negative voltage.

6 more elements

A step-up apparatus comprising:

a first level shift circuit for receiving a clock first signal to generate two phase-opposite second clock signals;
a second level shift circuit for receiving said first clock signal to generate two phase-opposite third clock signals;
a charge pump circuit, connected to said first level shift circuit, for stepping up a power supply voltage at a power supply voltage terminal using said second clock signals to generate first and second positive voltages, said first positive voltage being smaller than said second positive voltage;
and
a polarity inverting circuit, connected to said charge pump circuit and said second level shift circuit, for inverting said second positive voltage using said third clock signals to generate a negative voltage whose absolute value is the same as said second positive voltage,
a high level of said second clock signals being not higher than said second positive voltage,
a low level of said second clock signals being not lower than a voltage at a ground terminal,
a high level of said third clock signals being not higher than said power supply voltage,
a low level of said third clock signals being not lower than said negative voltage.

6 more elements

A step-up apparatus comprising:

a first level shift circuit for receiving a clock first signal to generate two phase-opposite second clock signals;
a second level shift circuit for receiving said first clock signal to generate a third clock signal;
a charge pump circuit, connected to said first level shift circuit, for stepping up a power supply voltage at a power supply voltage terminal using said second clock signals to generate first and second positive voltages;
and
a polarity inverting circuit, connected to said charge pump circuit and said second level shift circuit, for inverting said second positive voltage using said third clock signal to generate a negative voltage whose absolute value is the same as said second positive voltage,
a high level of said second clock signals being not higher than said second positive voltage,
a low level of said second clock signals being not lower than a voltage at a ground terminal,
a high level of said third clock signal being not higher than said voltage at said ground voltage,
a low level of said third clock signal being not lower than said negative voltage.

6 more elements

A step-up apparatus comprising:

a first level shift circuit for receiving a clock first signal to generate two phase-opposite second clock signals;
a second level shift circuit for receiving said first clock signal to generate two phase-opposite third clock signals;
a charge pump circuit, connected to said first level shift circuit, for stepping up a power supply voltage at a power supply voltage terminal using said second clock signals to generate first and second positive voltages, said first positive voltage being smaller than said second positive voltage;
and
a polarity inverting circuit, connected to said charge pump circuit and said second level shift circuit, for inverting said first positive voltage using said third clock signals to generate a negative voltage whose absolute value is the same as said first positive voltage,
a high level of said second clock signals being not higher than said first positive voltage,
a low level of said second clock signals being not lower than a voltage at a ground terminal,
a high level of said third clock signals being not higher than said power supply voltage,
a low level of said third clock signals being not lower than said negative voltage.

6 more elements

A step-up apparatus comprising:

a first level shift circuit for receiving a clock first signal to generate two phase-opposite second clock signals;
a second level shift circuit for receiving said first clock signal to generate a third clock signal;
a charge pump circuit, connected to said first level shift circuit, for stepping up a power supply voltage at a power supply voltage terminal using said second clock signals to generate first and second positive voltages;
and
a polarity inverting circuit, connected to said charge pump circuit and said second level shift circuit, for inverting said first positive voltage using said third clock signal to generate a negative voltage whose absolute value is the same as said first positive voltage,
a high level of said second clock signals being not higher than said first positive voltage,
a low level of said second clock signals being not lower than a voltage at a ground terminal,
a high level of said third clock signal being not higher than said voltage at said ground voltage,
a low level of said third clock signal being not lower than said negative voltage.

6 more elements

A step-up apparatus comprising:

a first level shift circuit for receiving a first clock signal to generate a 2nd clock signal, a 3rd clock signal, . . . , a K-th clock signal (K=2, 3, . . . ) having a definite voltage swing;
a second level shift circuit for receiving said first clock signal to generate two phase-opposite third clock signals;
a charge pump circuit, connected to said first level shift circuit, for stepping up a power supply voltage at a power supply voltage terminal using said first, second, . . . , K-th clock signals to generate a positive voltage;
and
a polarity inverting circuit, connected to said charge pump circuit and said second level shift circuit, for inverting said positive voltage using said third clock signals to generate a negative voltage whose absolute value is the same as said positive voltage,

2 more elements

A step-up apparatus comprising:

a level shift circuit for receiving a first clock signal to generate a 2nd clock signal, a 3rd clock signal, . . . , a K-th clock signal (K=2, 3, . . . ) having a definite voltage swing;
and
a charge pump circuit, connected to said first level shift circuit, for stepping up a power supply voltage at a power supply voltage terminal using said first, second, . . . , K-th clock signals to generate a positive voltage.

Dependencies are inferred from the claim text.

Facts

Application: 10/684,441Filed 15 Oct 2003
Priority: JP 2002-30118616 Oct 2002
Published: 2 Sep 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H02M 3/073
Using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps: charge pumps of the…
H02M 1/009
Converters characterised by their input or output configuration: having two or more independently controlled outputs
H02M 3/071
Using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps: adapted to generate a…
H02M 3/076
Charge pumps of the Schenkel-type: the clock signals being boosted to a value being higher than the input voltage value

Family

US 7,005,912 B2Related patent
US 2004/0169548 A1This patent

From the US filing history. Foreign family members aren’t listed.

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