Low-jitter delay cell

A timing generator for use in a semiconductor tester, the timing generator including:

• a delay line having a plurality of delay cells with respective phase-shifted outputs, each of the delay cells including,
• a voltage bus;
• a differential pair of MOS transistors having respective source terminals coupled to define a current node, and respective drain terminal outputs that cooperate to form a differential output;
• a current source disposed at the current node;
• and
• a differential diode-connected load disposed between the differential pair and the voltage bus, the differential diode-connected load comprising at least one n-channel MOS transistor configured as a diode;
• a multiplexer having a plurality of inputs for receiving the phase shifted outputs, and an output;
• and
• phase detection circuitry for detecting the phase shift between the multiplexer output and a reference signal.

A method of delaying a timing signal through a delay cell, the delay cell including a voltage supply bus for providing VDD, the method comprising the steps:

• generating a bias current in the delay cell, the bias current controlling the amount of delay provided by the delay cell;
• detecting the timing signal with a differential switch;
• and
• establishing a negative-feedback path to compensate for voltage variations on the voltage supply bus.

A method of delay compensation for the effects of variations to VDD acting on the bias current of a differential delay cell, the method including the steps:

• establishing a first bias current through the delay cell to achieve a desired delay characteristic for the delay cell;
• detecting changes to VDD;
• and
• compensating for any effects on the bias current based on the changes to VDD.