Miller effect compensation technique for DLL phase interpolator design
OwnerClaude R. Gauthier, Brian W. Amick +1inventors
InventorsClaude R. Gauthier, Brian W. Amick, Dean Liu
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Abstract
A delay locked loop design uses a fixed capacitance to load down a signal output from a phase selector of the delay locked loop to a phase interpolator of the delay locked loop. Such loading counteracts for variable capacitive coupling that occurs in the phase interpolator as interpolation weights to the phase interpolator change. Without such loading of the output of the phase selector, the delay of the phase selector varies as a function of the capacitance coupling of the phase interpolator.
Claims20
An integrated circuit, comprising:
- a phase selector stage arranged to receive phase shifted signals and output at least a pair of the phase shifted signals;
- at least one signal wire arranged to propagate the at least a pair of the phase shifted signals;
- a phase interpolator stage having an input operatively connected to the at least one signal wire, wherein the phase interpolator stage is arranged to receive the at least a pair of the phase shifted signals and interpolate between the at least a pair of the phase shifted signals;
- and
- at least one capacitor operatively connected to the at least one signal wire.
An integrated circuit, comprising:
- means for generating phase shifted signals dependent on an input clock signal;
- means for selecting at least a pair of the phase shifted signals;
- means for propagating the selected at least a pair of the phase shifted signals;
- means for interpolating between the selected at least a pair of the phase shifted signals;
- and
- means for loading the means for propagating such that the means for interpolating does not substantially load the means for selecting.
A method for operating a delay locked loop, comprising:
- inputting a plurality of phase shifted differential signal pairs;
- selecting at least one of the phase shifted differential signal pairs;
- propagating the at least one selected phase shifted differential signal pair;
- interpolating between signals in the at least one selected phase shifted differential signal pair;
- and
- capacitively loading the propagating such that the interpolating does not substantially affect the selecting.
Dependencies are inferred from the claim text.