US 2004/0169538 A1 · DLL circuit

Abstract

DLL circuit with a small minimum delay time while allowing a wide range of adjustment of the delay time. The DLL circuit according includes a first delay circuit for delaying an input clock signal (CLK1) to output a plurality of delayed clock signals (T1 to TN), a first selector (7) for selecting a first delayed clock signal (CLK_E) and a second delayed clock signal (CLK_O) from among the plurality of delayed clock signals (T1 to TN), for output, a second delay circuit (3) for delaying the input clock signal (CLK1) to generate a slightly delayed clock signal (CLKD), a second selector (4) for selecting two selected clock signals (FDLE, FDLO) from among the slightly delayed clock signal (CLKD), first delayed clock signal (CLK_E), and second delayed clock signal (CLK_O), and a delay synthesis circuit (5) for generating an internal clock signal (CLKIN) from the selected clock signals (FDLE, FDLO), for output.

Claims12

Dependent claims

A Delay Locked Loop DLL circuit comprising:

a first delay circuit for delaying an input clock signal to output a plurality of delayed clock signals;
a first selector for selecting a first delayed clock signal and a second delayed clock signal from among the plurality of delayed clock signals, for output;
a second delay circuit for delaying the input clock signal to generate a slightly delayed clock signal;
a second selector for selecting two selected clock signals from among the slightly delayed clock signal, the first delayed clock signal, and the second delayed clock signal, for output;
and
a delay synthesis circuit for generating an internal clock signal from said selected clock signals, for output.

3 more elements

A DLL circuit comprising:

an input buffer for receiving an external clock signal and then generating an input clock signal;
a first delay circuit for delaying the input clock signal to output a plurality of delayed clock signals;
a first selector for selecting a first delayed clock signal and a second delayed clock signal from among the plurality of delayed clock signals, for output;
a second delay circuit for delaying said input clock signal to generate a first slightly delayed clock signal;
a third delay circuit for delaying an external clock signal to generate a second slightly delayed clock signal;
a second selector for selecting two selected clock signals from among the first slightly delayed clock signal, the second slightly delayed clock signal, the first delayed clock signal, and the second delayed clock signal, for output;
and
a delay synthesis circuit for synthesizing an internal clock signal from the selected clock signals, for output.

5 more elements

Dependencies are inferred from the claim text.

DLL circuit

Life of this patent

DLL circuit

Life of this patent

Abstract

Claims12