Semiconductor integrated circuit device

A semiconductor integrated circuit device has a first clock processing means to input a first clock and a second clock and generate a third clock, a second clock processing means to input a third clock and a fourth clock and generate a fifth clock, and a first latch group and a second latch group comprised of at least one latch, wherein the second clock is generated from the third clock by way of a buffer, the frequency of the second and third clocks are identical, the first clock processing means generates the third clock so that the first and second clocks will have an identical phase and frequency, a fourth clock is generated by way of a buffer from the fifth clock, the frequency of the fourth and fifth clocks are identical, the second clock processing means generates a fifth clock so that the third and fourth clocks will have an identical phase and identical frequency, the third clock is supplied by way of a buffer to the first latch group, the fifth clock is supplied by way of a buffer to the second latch group, and the first latch group and the second latch group operate at an identical phase.

A semiconductor integrated circuit device has a first clock processing means to input a first clock and a second clock and generate a third clock, a second clock processing means to input a third clock and a fourth clock and generate a fifth clock, and a first latch group and a second latch group comprised of at least one hatch wherein a second clock is generated from a third clock by way of a buffer or divider, the frequency of the second clock is lower than the frequency of the third clock, the first clock processing means generates a third clock so that the first and second clocks will have an identical phase and an identical frequency, a fourth clock is generated from a fifth clock by way of a buffer, the fourth clock and the fifth clock are identical frequencies, the second clock processing means generates a fifth clock so that the third and fourth clocks will have an identical phase and an identical frequency, a third clock is supplied by way of a buffer to the first latch group, a fifth clock is supplied by way of a buffer to the second latch group, and the first latch group and the second latch group operate at an identical phase.

A semiconductor integrated circuit device has a first clock processing means to input a first chock and a second clock and generate a third clock, a second clock processing means to input a third clock and a fourth chock and generate a fifth clock, and a first latch group and a second latch group comprised of at least one hatch wherein a second clock is generated from a third clock by way of a buffer or divider, the frequency of the second clock is lower than the frequency of the third clock, the first clock processing means generates a third clock so that the first and second clocks will have an identical phase and an identical frequency, a fourth clock is generated from a fifth clock by way of a buffer and divider, the fourth clock frequency is lower than the fifth clock frequency, the second chock processing means generates a fifth clock so that the third and fourth clocks will have an identical phase and an identical frequency, a third clock is supplied by way of a buffer to the first latch group, a fifth clock is supplied by way of a buffer to the second latch group, and the first hatch group and the second latch group operate at an identical phase.

A circuit design method to read out design data for a first circuit block from a record medium stored with design data for a first circuit block and combine with a second circuit block design data to comprise design data for a single semiconductor integrated circuit device wherein a clock signal phase adjuster means is inserted between said first circuit block and said second circuit block.

A circuit design method provided with a first circuit block design data having a clock output terminal to output a clock signal, and a circuit to adjust the phase of the clock signal sent from said clock output terminal, and combine with a second circuit block design data wherein the clock output terminal of said first circuit block is connected to the clock input terminal of said second circuit block.

A record medium for storing circuit design data wherein said record medium has a clock input terminal to receive a clock signal, a circuit to adjust the phase of the clock signal sent from said clock input terminal, and an internal circuit controlled by said adjusted clock signal.

A data distribution method provided with a recording medium for storing circuit design data and said record medium has a clock input terminal to receive a clock signal, a circuit to adjust the phase of the clock signal sent from said clock input terminal, and an internal circuit controlled by said adjusted clock signal wherein said circuit data from said record medium is sent to a user in response to a request from said user for transfer of data.

An electrical circuit having a clock generator to supply clock signals, a plurality of first controlled circuits supplied with clock signals from said clock generator and clock signal phase adjuster circuits, a second controlled circuit supplied with clock signals passed through said clock signal phase adjuster circuits wherein the number of first controlled circuits supplied by clock pulses from said clock generator is larger than the number of clock signal phase adjuster circuits.

An electrical circuit having a clock generator to supply clock signals, a plurality of first controlled circuits supplied with clock signals from said clock-generator and clock signal phase adjuster circuits, a second controlled circuit supplied with clock signals passed through said clock signal phase adjuster circuits wherein the percentage occupied by said first control circuits from among the fan-out from the clock generator is larger than the percentage of clock signal phase adjuster circuits.

An electrical circuit having a signal clock generator for supplying signals of a specified frequency, a plurality of first latch circuits and said phase adjuster circuits supplied with signals from said signal clock generator, and a plurality of second hatch circuits supplied with signals passed through said signal phase adjuster circuits wherein the percentage occupied by said first latch circuits from among the fan-out from the signal clock generator is larger than the percentage of clock signal phase adjuster circuits.