Frequency division/multiplication with jitter minimization
AssigneeBroadcom Corporation
InventorsSiavash Fallahi, Myles Wakayama, Pieter Vorenkamp
Life of this patent
Estimating the term…
Abstract
A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.
Claims16
A method comprising:
- (a) using a phase-lock loop (PLL) to produce M clock phases from a reference signal;
- (b) producing a count signal from the M clock phases;
- (c) producing a shifted signal from the M clock phases and the count signal;
- and
- (d) dividing the shifted signal to produce a feedback signal that is fed back to the PLL.
A method comprising:
- (a) receiving a reference signal and a feedback signal at a clock generator;
- (b) using the clock generator to generate M clock phases from at least one of the reference signal and the feedback signal;
- (c) generating a count signal from the M clock phases;
- (d) generating a shifted signal from the M clock phases and the count signal;
- and
- (e) dividing the shifted signal to produce the feedback signal.
Dependencies are inferred from the claim text.