Apparatus, generator, and method for clock tree synthesis
AssigneeSamsung Electronics Co., Ltd.
InventorsMi-Sook Jang, Hoi-Jin Lee
Life of this patent
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Abstract
A clock tree synthesis (CTS) apparatus, generator, and method for synthesizing a clock tree includes a plurality of clock signal generators that output different clock signals generated from a reference clock signal. The clock signal generators includes an additional logic circuit that is not recognized as an end point of the reference clock signal when the clock tree is synthesized. In one example, the clock signal generator is a flip-flop and the additional logic circuit is a tri-state buffer.
Claims18
A clock tree synthesis (CTS) apparatus for synthesizing a clock tree, the CTS apparatus comprising:
- at least one clock generator that outputs a clock signal different from a reference clock signal, the at least one clock generator including an additional circuit that is not recognized as an end point of the reference clock signal when the clock tree is synthesized.
A clock signal generator comprising:
- a flip-flop;
- and
- an additional circuit that is not recognized as an end point of a reference clock signal when a clock tree is synthesized.
A method for synthesizing a clock tree comprising:
- generating a reference clock signal;
- generating a plurality of clock signals with different timing from the reference clock signal;
- introducing at least one delay to compensate for the different timings;
- and
- synthesizing a clock tree from the compensated different timings.
A method for synthesizing a clock tree using a clock tree synthesis (CTS) apparatus including at least one clock generator that outputs a clock signal different from a reference clock signal, the at least one clock generator including an additional circuit that is not recognized as an end point of the reference clock signal when the clock tree is synthesized, the method comprising:
- generating a reference clock signal;
- generating a plurality of clock signals with different timing from the reference clock signal;
- introducing at least one delay to compensate for the different timings;
- and
- synthesizing a clock tree from the compensated different timings.
A method for synthesizing a clock tree using a clock signal generator including a flip-flop and an additional circuit that is not recognized as an end point of a reference clock signal when a clock tree is synthesized, the method comprising:
- generating a reference clock signal;
- generating a plurality of clock signals with different timing from the reference clock signal;
- introducing at least one delay to compensate for the different timings;
- and
- synthesizing a clock tree from the compensated different timings.
Dependencies are inferred from the claim text.