US 2004/0169527 A1 · Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit

Abstract

To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit is composed by a semiconductor logic circuit wherein the number of columns of transistors for pulling down at an output node is small even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. According to the present invention, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and in a semiconductor memory for example, the reduction of access time and power consumption and the increase of the cycles are enabled.

Claims28

Dependent claims

A semiconductor integrated circuit, wherein:

a buffer circuit from which the true and a complementary signal are output based upon input signals and a decoder circuit for decoding based upon signals output from said buffer circuit are provided;
a semiconductor logic circuit in which at least one of said buffer circuit and said decoder circuit is controlled for precharge and evaluation operation according to the polarity of a control signal input to its control terminal and the true and a complementary signal are output based upon input signals input to its input terminals is provided;
and
said semiconductor logic circuit of said decoder circuit is composed of a set in which an output signal including said true of any of plural said buffer circuits is input to its control terminal and a set to which a complementary output signal is input, and output signals from the other buffer circuits are input to the input terminal of said semiconductor logic circuit of said decoder circuit.

1 more element

A semiconductor logic circuit, comprising:

a first load provided between a first power source terminal and a first node and controlled by a control signal and a second load provided with said first power source terminal and a second node and controlled by said control signal;
a logic circuit for input provided between said first node and a third node for electrically connecting said first node and said third node according to an input signal;
a field effect transistor for reference paths to the source and the drain of which are provided between said second node and said third node and the gate of which is connected to said first node;
and
an activation circuit provided between said third node and a second power source terminal and controlled by said control signal, wherein:
a reset circuit for reducing the pulse length of a signal output from said semiconductor logic circuit is provided.

3 more elements

Dependencies are inferred from the claim text.

Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit

Life of this patent

Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit

Life of this patent

Abstract

Claims28