On-chip ADC test for image sensors
AssigneeMicron Technology, Inc.
InventorKwang-Bo Cho
Life of this patent
Estimating the term…
Abstract
The speed of on-chip ADC testing of image sensors is increased by testing multiple chips in parallel. A wafer typically contains many individual image sensor chips. In a parallel on-chip test procedure, power is applied to a plurality of the image sensor chips and the chips are then tested in parallel. Additional power lines may need to be added to the wafer to allow power to be supplied to a plurality of the image sensor chips at once. These power lines may be etched directly on the wafer, or a wafer master may be used to overlay the wafer with the power lines for testing purposes. Additionally, test engines may be added to the wafer map to control the overall test procedures.
Claims24
A method of simultaneously testing analog-to-digital converters (ADC) on a plurality of chips on a wafer comprising:
- connecting a first group of the plurality of chips to a first power line and connecting a second group of plurality of chips to a second power line;
- applying a power signal to said first power line;
- simultaneously running ADC test procedures on each of said first group of chips connected to said first of the power lines during said applying;
- and
- reporting test results for each of the chips in the first group.
A wafer comprising:
- a plurality of chips, wherein each of the plurality of chips includes an analog-to-digital converter;
- one or more power lines connecting at least a portion of the plurality of chips, wherein the one or more power lines interconnect the portion of the plurality of chips to simultaneously run ADC test procedures on each chip in the portion of the plurality of chips.
A wafer test system comprising:
- a wafer including a plurality of chips, wherein each of the plurality of chips includes an analog-to-digital converter (ADC);
- a template including one or more power lines and a plurality of vias which correspond to the plurality of chips on the wafer, wherein the template is adapted to interface with the wafer so the one or more power lines interconnect at least a portion of the plurality of chips to simultaneously run ADC test procedures on each chip in the portion of the plurality of chips.
An assembly, comprising:
- a wafer including a plurality of separable image elements thereon, arranged in groups, each group having a plurality of said image elements therein;
- a plurality of power lines, one of said power lines arranged for each group, and arranged to provide a connection for power to each of said image elements in each of said group;
- a testing element, connectable to a plurality of said image elements, and operable when connected to said image elements to test each of said image elements in the group and report a result of said test.
An assembly, comprising:
- a wafer, including a plurality of separable image elements arranged in a linear direction;
- a first power line, also arranged linearly, and arranged adjacent to a first group of said image elements, said first group collectively forming a linearly shaped group adjacent to said first power line;
- a second power line, arranged linearly but spaced from said first power line, and arranged adjacent to a second group of said image elements, said second group collectively forming a linearly shaped group adjacent to said first power line but spaced from said first group;
- a test structure, connected to one of said groups, and operable to test each of the image elements in said one of said groups during a time period When said one of said groups is receiving power.
Dependencies are inferred from the claim text.