Field emission display having reduced power requirements and method

A field emission display baseplate comprising:

• a substrate;
• a plurality of conductors formed on the substrate;
• a plurality of emitters each formed on one of the plurality of conductors;
• a porous silicon dioxide layer formed by anodization on the substrate and the conductors;
• an extraction grid formed on the dielectric layer and including an opening;
• an opening formed in the dielectric layer coaxial with the opening in the extraction grid;
• an emitter body comprising a high resistivity material formed in the opening in the porous silicon dioxide layer;
• and
• an emitter tip formed on the emitter body and in the extraction grid opening, the tip formed from a material having a work function or electron affinity of less than four electron volts.

A field emission display baseplate comprising:

• a substrate;
• a plurality of spaced-apart conductors formed on the substrate;
• a porous silicon dioxide layer formed on the substrate and the conductors by a modification of a silicon layer;
• an extraction grid formed on the porous silicon dioxide layer and including an opening;
• an opening formed in the porous silicon dioxide layer coaxial with the opening in the extraction grid;
• and
• an emitter formed in the opening in the porous silicon dioxide layer and in the extraction grid opening.

A field emission display comprising:

• a substrate;
• a plurality of emitters formed on the substrate, each of the emitters being formed on a conductor;
• a porous dielectric layer formed on the substrate, the porous dielectric layer having an opening formed about each of the emitters, the porous dielectric layer having a thickness substantially equal to a height of the emitters above the substrate, the porous layer formed by oxidation of porous silicon;
• an extraction grid extraction grid formed substantially in a plane defined by respective tips of the plurality of emitters and having an opening surrounding each tip of a respective one of the emitters;
• and
• a cathodoluminescent-coated faceplate having a planar surface formed parallel to and near the plane of tips of the plurality of emitters.

A computer system comprising:

• a central processing unit;
• a memory device coupled to the central processing unit, the memory device storing instructions and data for use by the central processing unit;
• an input interface;
• and
• a display, the display comprising:
• a cathodoluminescent layer formed on a conductive surface of a transparent faceplate;
• a substrate disposed parallel to and near the cathodoluminescent layer formed on the faceplate;
• a plurality of conductors formed on the substrate;
• a plurality of emitters formed on the conductors;
• a porous silicon dioxide layer formed on the substrate and the columns, the porous silicon dioxide layer including openings each formed about one of the emitters, the porous layer formed by oxidation of porous silicon;
• and
• an extraction grid formed on the porous silicon dioxide layer and including openings each coaxial with one of the openings in the porous silicon dioxide layer.

A method of fabricating a field emission display baseplate comprising:

• forming columns on a substrate;
• forming a layer of silicon on the columns and the substrate;
• etching the silicon layer to form a layer of porous silicon;
• oxidizing the porous silicon layer to form a layer of porous silicon dioxide;
• forming an extraction grid on the porous silicon dioxide layer;
• etching openings through the porous silicon dioxide and the extraction grid;
• and
• forming emitters in the openings in the porous silicon dioxide and the extraction grid.

A method of fabricating a porous dielectric layer in a field emission display comprising:

• forming a polycrystalline silicon layer on a substrate and a plurality of columns on the substrate;
• forming pores in the polycrystalline silicon layer;
• and
• oxidizing the polycrystalline silicon layer to provide a porous silicon dioxide layer.

A method of fabricating a field emission display baseplate comprising:

• forming conductors on a substrate;
• forming a layer of silicon dioxide on the conductors and on the substrate;
• forming an extraction grid on the porous silicon dioxide layer;
• etching openings through the silicon dioxide and the extraction grid;
• and
• forming emitters in the openings in the porous silicon dioxide and the extraction grid.