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US 2004/0169293 A1Published application
Basic cells configurable into different types of semiconductor integrated circuits
AssigneeOki Electric Industry Co., Ltd.
InventorAkihiro Sushihara
Life of this patent
Estimating the term…
Abstract
The basic cell constituted by a semiconductor integrated circuit comprises two PMOS transistors and two NMOS transistors. By setting the gate widths of the gates of these transistors to prescribed lengths, the efficiency of use of elements within the basic cell is improved, and fine adjustment of the threshold voltage Vth and delay time Tpd becomes possible.
Claims12
A semiconductor integrated circuit, manufactured by forming wiring on a bulk chip comprising a plurality of basic cells arranged in an array, wherein:
- said basic cells comprise first and second P-channel MOS transistors, and first and second N-channel MOS transistors;
- said second P-channel MOS transistor and said first P-channel MOS transistor are juxtaposed;
- said second N-channel MOS transistor and said first N-channel MOS transistor are juxtaposed;
- the gates of each of said transistors are parallel to each other;
- the gate of said first P-channel MOS transistor and the gate of said first N-channel MOS transistor are provided in a line;
- the gate of said second P-channel MOS transistor and the gate of said second N-channel MOS transistor are provided in a line;
- and,
- the gate width W1 of the gate of said first P-channel MOS transistor, the gate width W2 of the gate of said second P-channel MOS transistor, the gate width W3 of the gate of said first N-channel MOS transistor, and the gate width W4 of the gate of said second N-channel MOS transistor, are selected such that
- W1:W2:W3:W4=2:2:1:1.
6 more elements
A semiconductor integrated circuit, manufactured by forming wiring on a bulk chip comprising a plurality of basic cells arranged in an array, wherein:
- said basic cells comprise first, second and third P-channel MOS transistors, and first and second N-channel MOS transistors;
- said second and third P-channel MOS transistors and said first P-channel MOS transistor are juxtaposed;
- said second N-channel MOS transistor and said first N-channel MOS transistor are juxtaposed;
- the gates of each of said transistors are parallel to each other;
- the gate of said second P-channel MOS transistor and the gate of said third P-channel MOS transistor are connected in a line;
- the gate of said first P-channel MOS transistor and the gate of said first N-channel MOS transistor are provided in a line;
- the gate of said third P-channel MOS transistor and the gate of said second N-channel MOS transistor are provided in a line;
- and,
- the gate width W1 of the gate of said first P-channel MOS transistor, the gate width W2 of the gate of said second P-channel MOS transistor, the gate width W3 of the gate of said third P-channel MOS transistor, the gate width W4 of the gate of said first N-channel MOS transistor, and the gate width W5 of the gate of said second N-channel MOS transistor, are, substantially, selected such that
- W1:W2:W3:W4:W5=2:1:1:1:1.
7 more elements
A semiconductor integrated circuit, manufactured by forming wiring on a bulk chip comprising a plurality of basic cells arranged in an array, wherein:
- said basic cells comprise first, second, third and fourth P-channel MOS transistors, and first and second N-channel MOS transistors;
- said second P-channel MOS transistor and said first P-channel MOS transistor are juxtaposed;
- said third P-channel MOS transistor and said fourth P-channel MOS transistor are juxtaposed;
- said second N-channel MOS transistor and said first N-channel MOS transistor are juxtaposed;
- the gates of each of said transistors are parallel to each other;
- the gate of said first P-channel MOS transistor and the gate of said third P-channel MOS transistor are connected in a line;
- the gate of said second P-channel MOS transistor and the gate of said fourth P-channel MOS transistor are connected in a line;
- the gate of said third P-channel MOS transistor and the gate of said first N-channel MOS transistor are provided in a line;
- the gate of said fourth P-channel MOS transistor and the gate of said second N-channel MOS transistor are provided in a line;
- and,
- the gate width W1 of the gate of said first P-channel MOS transistor, the gate width W2 of the gate of said second P-channel MOS transistor, the gate width W3 of the gate of said third P-channel MOS transistor, the gate width W4 of the gate of said fourth P-channel MOS transistor, the gate width W5 of the gate of said first N-channel MOS transistor, and the gate width W6 of the gate of said second N-channel MOS transistor, are selected such that
- W1:W2:W3:W4:W5:W6=1:1:1:1:1:1.
9 more elements
A semiconductor integrated circuit, manufactured by forming wiring on a bulk chip comprising a plurality of basic cells arranged in an array, wherein:
- said basic cells comprise first, second, third, fourth and fifth P-channel MOS transistors, and first and second N-channel MOS transistors;
- said second and third P-channel MOS transistors and said first P-channel MOS transistor are juxtaposed;
- said fifth P-channel MOS transistor and said fourth P-channel MOS transistor are juxtaposed;
- said second N-channel MOS transistor and said first N-channel MOS transistor are juxtaposed;
- the gates of each of said transistors are parallel;
- the gate of said first P-channel MOS transistor and the gate of said fourth P-channel MOS transistor are connected in a line;
- the gate of said second P-channel MOS transistor and the gate of said third P-channel MOS transistor and the gate of said fifth P-channel MOS transistor are connected in a line;
- the gate of said fourth P-channel MOS transistor and the gate of said first N-channel MOS transistor are provided in a line;
- the gate of said fifth P-channel MOS transistor and the gate of said second N-channel MOS transistor are provided in a line;
- and,
- the gate width W1 of the gate of said first P-channel MOS transistor, the gate width W2 of the gate of said second P-channel MOS transistor, the gate width W3 of the gate of said third P-channel MOS transistor, the gate width W4 of the gate of said fourth P-channel- MOS transistor, the gate width W5 of the gate of said fifth P-channel MOS transistor, the gate width W6 of the gate of said first N-channel MOS transistor, and the gate width W7 of the gate of said second N-channel MOS transistor, are selected such that
- W1:W2:W3:W4:W5:W6:W7=1:1/3:1/3:1:1:1:1.
9 more elements
A semiconductor integrated circuit, manufactured by forming wiring on a bulk chip comprising a plurality of basic cells arranged in an array, wherein:
- said basic cells comprise first, second, third, fourth, fifth and sixth P-channel MOS transistors, and first and second N-channel MOS transistors;
- said second P-channel MOS transistor and said first P-channel MOS transistor are juxtaposed;
- said fourth P-channel MOS transistor and said third P-channel MOS transistor are juxtaposed;
- said sixth P-channel MOS transistor and said fifth P-channel MOS transistor are juxtaposed;
- said second N-channel MOS transistor and said first N-channel MOS transistor are juxtaposed;
- the gates of each of said transistors are parallel;
- the gate of said first P-channel MOS transistor and the gate of said third P-channel MOS transistor and the gate of said fifth P-channel MOS transistor are connected in a line;
- the gate of said second P-channel MOS transistor and the gate of said fourth P-channel MOS transistor and the gate of said sixth P-channel MOS transistor are connected in a line;
- the gate of said fifth P-channel MOS transistor and the gate of said first N-channel MOS transistor are provided in a line;
- the gate of said sixth P-channel MOS transistor and the gate of said second N-channel MOS transistor are provided in a line;
- and,
- the gate width W1 of the gate of said first P-channel MOS transistor, the gate width W2 of the gate of said second P-channel MOS transistor, the gate width W3 of the gate of said third P-channel MOS transistor, the gate width W4 of the gate of said fourth P-channel MOS transistor, the gate width W5 of the gate of said fifth P-channel MOS transistor, the gate width W6 of the gate of said sixth P-channel MOS transistor, the gate width W7 of the gate of said first N-channel MOS transistor, and the gate width W8 of the gate of said second N-channel MOS transistor, are selected such that
- W1:W2:W3:W4:W5:W6:W7:W8=1/3:1/3:1/3:1/3:1:1:1:1.
10 more elements
A semiconductor integrated circuit, manufactured by forming wiring on a bulk chip comprising a plurality of basic cells arranged in an array, wherein:
- said basic cells comprise first, second, third, fourth, fifth and sixth P-channel MOS transistors, and first, second, third and fourth N-channel MOS transistors;
- said second P-channel MOS transistor and said first P-channel MOS transistor are juxtaposed;
- said fourth P-channel MOS transistor and said third P-channel MOS transistor are juxtaposed;
- said sixth P-channel MOS transistor and said fifth P-channel MOS transistor are juxtaposed;
- said second N-channel MOS transistor and said first N-channel MOS transistor are juxtaposed;
- said fourth N-channel MOS transistor and said third N-channel MOS transistor are juxtaposed;
- the gates of each of said transistors are parallel;
- the gate of said first P-channel MOS transistor and the gate of said third P-channel MOS transistor and the gate of said fifth P-channel MOS transistor are connected in a line;
- the gate of said second P-channel MOS transistor and the gate of said fourth P-channel MOS transistor and the gate of said sixth P-channel MOS transistor are connected in a line;
- the gate of said first N-channel MOS transistor and the gate of said third N-channel MOS transistor are connected in a line;
- the gate of said second N-channel MOS transistor and the gate of said fourth N-channel MOS transistor are connected in a line;
- the gate of said fifth P-channel MOS transistor and the gate of said first N-channel MOS transistor are provided in a line;
- the gate of said sixth P-channel MOS transistor and the gate of said second N-channel MOS transistor are provided in a line;
- and,
- the gate width W1 of the gate of said first P-channel MOS transistor, the gate width W2 of the gate of said second P-channel MOS transistor, the gate width W3 of the gate of said third P-channel MOS transistor, the gate width W4 of the gate of said fourth P-channel MOS transistor, the gate width W5 of the gate of said fifth P-channel MOS transistor, the gate width W6 of the gate of said sixth P-channel MOS transistor, the gate width W7 of the gate of said first N-channel MOS transistor, the gate width W8 of the gate of said second N-channel MOS transistor, the gate width W9 of the gate of said third N-channel MOS transistor, and the gate width W10 of the gate of said fourth N-channel MOS transistor, are selected such that
- W1:W2:W3:W4:W5:W6:W7:W8:W9:W10=1/3:1/3:1/3:1/3:1:1:1/2:1/2:1/3:1/3.
13 more elements
Dependencies are inferred from the claim text.