Integrated circuit devices and methods of forming the same that have a low dielectric insulating interlayer between conductive structures

A method of forming an integrated circuit device, comprising:

• providing a substrate;
• forming a pair of conductive structures on the substrate;
• forming a carbon-containing silicon oxide layer on the substrate between the pair of conductive structures;
• and
• forming a silicon oxide layer on the carbon-containing silicon oxide layer.

A method for forming a thin film of a semiconductor device comprising:

• forming a carbon-containing silicon oxide layer on a substrate and on conductive structures formed on the substrate using a methyl-silane based gas and a first hydrogen peroxide gas to fill a recess between the conductive structures with the carbon-containing silicon oxide layer;
• forming a silicon oxide layer on the carbon-containing silicon oxide layer using a silane based gas and a second hydrogen peroxide gas, wherein the silicon oxide layer has an upper surface higher than that of the conductive structures;
• and
• polishing the silicon oxide layer and the carbon-containing silicon oxide layer to expose the upper surface of the conductive structures.

A method for forming an insulating interlayer of a semiconductor device comprising:

• forming conductive structures having a conductive layer pattern and a nitride layer pattern on a substrate to form a recess between the conductive structures;
• forming a carbon-containing silicon oxide layer on the substrate and the conductive structures using a methyl-silane based gas and a first hydrogen peroxide gas to fill the recess with the carbon-containing silicon oxide layer;
• forming a silicon oxide layer on the carbon-containing silicon oxide layer using a silane based gas and a second hydrogen peroxide gas, wherein the silicon oxide layer has an upper surface higher than that of the conductive structures;
• and
• polishing the silicon oxide layer and the carbon-containing silicon oxide layer until the upper surface of the conductive structures is exposed to form an insulating interlayer comprising the carbon-containing silicon oxide layer and a remaining silicon oxide layer in the recess.

A method for forming an insulating interlayer of a semiconductor device comprising:

• forming conductive structures having a conductive layer pattern and a nitride layer pattern on a substrate to form a recess between the conductive structures;
• reacting a methyl-silane based gas with a first hydrogen peroxide gas over the conductive structures to form a carbon-containing silicon oxide layer on the substrate and the conductive structures, wherein the recess is filled with the carbon-containing silicon oxide layer;
• reacting a silane based gas with a second hydrogen peroxide gas to form a silicon oxide layer on the carbon-containing silicon oxide layer, wherein the silicon oxide layer has an upper surface higher than that of the conductive structures;
• and
• polishing the silicon oxide layer and the carbon-containing silicon oxide layer until the upper surface of the structures is exposed to form an insulating interlayer having the carbon-containing silicon oxide layer and a remaining silicon oxide layer in the recess.

A method for planarizing a semiconductor device comprising:

• loading a substrate having conductive patterns into a chamber, wherein the conductive patterns include a conductive layer and a silicon nitride layer that form a recess therebetween;
• reacting a methyl-silane based gas with a first hydrogen peroxide gas in the chamber to form a carbon-containing silicon oxide layer on the substrate and the conductive patterns, wherein the recess is filled with the carbon-containing silicon oxide layer;
• reacting a silane based gas with a second hydrogen peroxide gas to form a silicon oxide layer on the carbon-containing silicon oxide layer;
• and
• polishing the silicon oxide layer through a chemical mechanical polishing process using a slurry, wherein the slurry has a polishing selectivity between the silicon oxide layer and the silicon nitride layer.