Semiconductor devices and methods for manufacturing the same
AssigneeSeiko Epson Corporation
InventorsKazuki Matsumoto, Yukio Morozumi, Michio Asahina
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Abstract
Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The pad section 30A includes a wetting layer 32 and a metal wiring layer 37. The metal wiring layer 37 includes an alloy layer 34 that contacts the wetting layer 32. The alloy layer 34 is formed from a material composing the wetting layer 32 and a material composing the metal wiring layer 37.
Claims11
A semiconductor device comprising:
- a pad section over an interlayer dielectric layer,
- wherein the pad section includes a wetting layer and a metal wiring layer, and
- the metal wiring layer includes an alloy layer that contacts the wetting layer, the alloy layer including a material that forms the wetting layer and a material that forms the metal wiring layer.
A semiconductor device according to claim 2, wherein the metal wiring layer is formed from aluminum or an aluminum alloy.
A semiconductor device, comprising:
- an interlayer dielectric on a substrate;
- a wetting layer material on the interlayer dielectric layer;
- an alloy layer on the wetting layer material;
- a metal layer on the alloy layer;
- wherein the metal layer includes aluminum;
- wherein the alloy layer includes the wetting layer material and aluminum;
- and
- wherein the alloy layer has a thickness that is two to three times greater than that of the wetting layer.
Dependencies are inferred from the claim text.