Semiconductor wafer having separation groove on insulating film on dicing line region and its manufacturing method
AssigneeKabushiki Kaisha Toshiba
InventorToshitsune Iijima
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Abstract
A semiconductor wafer includes a plurality of element-forming regions, a dicing line region and an insulating film. The dicing line region separates the element-forming regions from each other. The insulating film covers the element-forming regions and the dicing line region. The insulating film insulating film is formed of multi-layered insulating layers which insulate respective wiring layers of a multi-layer form. A separation region is formed at least in a portion of the insulating film located on the dicing line region, so that the separation region separates the insulating film on the dicing line region from the insulating film on the element-forming regions.
Claims20
A semiconductor wafer comprising:
- a plurality of element-forming regions;
- a dicing line region which separates the element-forming regions from each other;
- and
- an insulating film which covers the element-forming regions and the dicing line region, the insulating film being formed of multi-layered insulating layers which insulate respective wiring layers of a multi-layer form,
- wherein a separation region is formed at least in a portion of the insulating film located on the dicing line region, the separation region separating the insulating film on the dicing line region from the insulating film on the element-forming regions.
A method of producing a semiconductor wafer, comprising:
- forming a plurality of element-forming regions separated from each other by a dicing line region, the element-forming regions each having a semiconductor element;
- covering the element-forming regions and the dicing line region with an insulating film, the insulating film being formed of multi-layered insulating layers which insulate respective wiring layers of a multi-layer form;
- and
- forming a separation region at least in a portion of the insulating film located on the dicing line region, the separation region separating the insulating film on the dicing line region from the insulating film on the element-forming regions.
A semiconductor chip comprising:
- an element-forming region in which a semiconductor element is formed;
- a dicing line region which surrounds the element-forming regions;
- and
- an insulating film which covers the element-forming region and the dicing line region, the insulating film being formed of multi-layered insulating layers which insulate respective wiring layers of a multi-layer form,
- wherein a separation region is formed at least in a portion of the insulating film located on the dicing line region, the separation region separating the insulating film on the dicing line region from the insulating film on the element-forming region.
Dependencies are inferred from the claim text.