Multiple gate MOSFET structure with strained Si Fin body

A method for fabricating a tensilely strained Si multifaceted-gate MOSFET (FinFET) device, comprising the steps of:

• providing a monocrystalline relaxed SiGe layer, said SiGe layer having at least one sidewall surface, a top surface, and a bottom surface, wherein said bottom surface is bonded to a support platform;
• growing by selective epitaxy a monocrystalline Si strip onto said at least one SiGe sidewall surface, and wherein said Si strip is bonded to said support platform, whereby said Si strip is in a tensilely strained state;
• removing said SiGe layer, whereby said monocrystalline Si strip is turned into a multifaceted Si strip bonded to said support platform;
• and
• completing said FinFET processing steps on said multifaceted Si strip.

A method for building a processor, comprising the steps of:

• (a) producing logic circuits on a surface of at least one chip, comprising the steps of:
• (1) fabricating a plurality of tensilely strained Si multifaceted-gate MOSFET (FinFET) devices on said surface of at least one chip, comprising the steps of:
• providing plurality of monocrystalline relaxed SiGe layers, said SiGe layers having each at least one sidewall surface, a top surface, and a bottom surface, wherein each said bottom surface is bonded to a support platform;
• growing by selective epitaxy a monocrystalline Si strip onto each of said at least one SiGe sidewall surface, and wherein each of said Si strip is bonded to said support platform, whereby each of said Si strip is in a tensilely strained state;
• removing each of said SiGe layer, whereby each of said monocrystalline Si strip is turned into a multifaceted Si strip bonded to said support platform;
• completing said FinFET processing steps on each of said multifaceted Si strips;
• (2) interconnecting said FinFET devices into said logic circuits on said surface of at least one chip;
• and
• (b) interconnecting said logic circuits according to a specified design of said processor.