Transistor storing multiple bits and method of manufacturing semiconductor memory including the same

A transistor comprising:

• a one-conductivity type semiconductor substrate formed with a projection having a pair of side walls facing each other;
• a first insulation layer formed on a top of the projection;
• a pair of counter-conductivity type source/drain regions formed on a surface of said semiconductor substrate at both sides of the projection;
• second insulation layers each covering one of the pair of side walls and one of said source/drain regions;
• a pair of floating gates respectively formed on the pair of side walls of the projection and respectively facing the side walls and said source/drain regions via respective second insulation layers;
• third insulation layers each being formed on one of said floating gates;
• and
• a control gate facing said pair of floating gates via said third insulation layers and facing the top of the projection via said first insulation layer;
• wherein a surface of each of said pair of floating gates, facing said control gate via one of said third insulation layers, has a smaller area than a surface of said floating gate facing one of said pair of source/drain regions via one of said second insulation layers.

A method of manufacturing a transistor, comprising the steps of:

• (a) forming a plurality of trenches in a primary surface of a one-conductivity type semiconductor substrate to thereby form a plurality of projections each having a pair of side walls that face each other;
• (b) implanting a counter-conductivity type impurity in bottoms of said plurality of trenches to thereby form source/drain regions on said bottoms;
• (c) forming second insulation layers on said source/drain regions and the side walls of each of said projections;
• (d) forming floating gates, each having a substantially square section, on the side walls of the projection and said source/drain regions via said second insulation layers;
• (e) forming a fourth insulation layer between said floating gate formed on one of the side walls of one of the projections, which adjoin each other, and said floating gate formed on the side wall of the other projection;
• and
• (f) forming third insulation layers on said fourth insulation layer and said floating gates, and forming a control gate on said third insulation layers.

A method of manufacturing a semiconductor memory, comprising the steps of:

• (a) forming a plurality of trenches in a primary surface of a one-conductivity type semiconductor substrate to thereby form a plurality of projections each having a pair of side walls that face each other;
• (b) implanting a counter-conductivity type impurity in bottoms of said plurality of trenches to thereby form source/drain regions on said bottoms;
• (c) forming second insulation layers on said source/drain regions and the side walls of each of said projections;
• (d) forming floating gates, each having a substantially L-shaped section, on the side walls of the projection and said source/drain regions via said second insulation layers;
• (e) forming a fourth insulation layer between said floating gate formed on one of the side walls of one of the projections, which adjoin each other, and said floating gate formed on the side wall of the other projection;
• and
• (f) forming third insulation layers on said fourth insulation layer and said floating gates, and forming a control gate on said third insulation layers.

In a semiconductor device comprising:

• a one-conductivity type semiconductor substrate;
• a first insulation layer formed on said semiconductor substrate;
• a first electrode formed via said first insulation layer by use of a semiconductor;
• a second insulation layer formed on said first electrode;
• and
• a second electrode formed on said first electrode via said second insulation layer by use of a semiconductor;
• a surface of said first electrode, facing said second electrode via said second insulation layer, is flattened by CMP.