Semiconductor storage location
AssigneeInfineon Technologies AG
InventorLars Bartholomaus
Life of this patent
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Abstract
In a semiconductor memory cell, in particular in a DRAM memory cell array, having a selection transistor (12) and a storage capacitor (14), in which the storage capacitor (14) has a first (16) and a second (18) capacitor electrode, the first capacitor electrode (16) is connected to a read-out line (22) via the selection transistor (12), and in which a control terminal (32) of the selection transistor (12) is connected to a control line (24), as a special feature a layer of a superionic conductor (20) is arranged between the first and second capacitor electrodes (16, 18) of the storage capacitor (14). The high conductivity of the superionic conductor (20) for ions in association with a negligible electron conductivity allows extremely high capacitances to be produced in a small space.
Claims7
A semiconductor memory cell, in particular in a DRAM memory cell array, having
- a selection transistor (12) and a storage capacitor (14),
- in which the storage capacitor (14) has a first (16) and a second (18) capacitor electrode,
- the first capacitor electrode (16) is connected to a read-out line (22) via the selection transistor (12), and
- in which a control terminal (32) of the selection transistor (12) is connected to a control line (24), characterized in that
- a layer of a superionic conductor is arranged between the first and second capacitor electrodes (16, 18) of the storage capacitor (14).
The semiconductor memory cell as claimed in one of the preceding claims, in which the superionic conductor layer (20) is formed from doped LAF3.
The semiconductor memory cell as claimed in one of the preceding claims, in which the storage capacitor (14) is formed as a trench capacitor.
Dependencies are inferred from the claim text.