Magnetic storage apparatus having dummy magnetoresistive effect element and manufacturing method thereof
AssigneeKabushiki Kaisha Toshiba
InventorsKentaro Nakajima, Minoru Amano
Life of this patent
Estimating the term…
Abstract
A magnetic memory device includes a memory cell portion, a peripheral circuit portion positioned in the vicinity of the memory cell portion, a plurality of first magnetoresistive effect elements which are arranged in the memory cell portion and function as memory elements, and a plurality of second magnetoresistive effect elements which are arranged in at least a part of the peripheral circuit portion and function as dummies, wherein a sum total of occupying areas of the second magnetoresistive effect elements is 5% to 80% of the peripheral circuit portion.
Claims35
A magnetic memory device comprising:
- a memory cell portion;
- a peripheral circuit portion positioned in the vicinity of the memory cell portion;
- a plurality of first magnetoresistive effect elements which are arranged in the memory cell portion and function as memory elements;
- and
- a plurality of second magnetoresistive effect elements which are arranged in at least a part of the peripheral circuit portion and function as dummies,
- wherein a sum total of occupying areas of the second magnetoresistive effect elements is 5% to 80% of the peripheral circuit portion.
A magnetic memory device comprising:
- a memory cell portion;
- a peripheral circuit portion positioned in the vicinity of the memory cell portion;
- a plurality of first magnetoresistive effect elements which are arranged in the memory cell portion and function as memory elements;
- and
- a plurality of second magnetoresistive effect elements which are arranged in the entire peripheral circuit portion and function as dummies,
- wherein a sum total of occupying areas of the second magnetoresistive effect elements is 5% to 80% of a predetermined area arbitrarily selected from the peripheral circuit portion.
A magnetic memory device comprising:
- a memory cell portion;
- a peripheral circuit portion positioned in the vicinity of the memory cell portion;
- a memory chip including the memory cell portion and the peripheral circuit portion;
- a plurality of first magnetoresistive effect elements which are arranged in the memory cell portion and function as memory elements;
- and
- a plurality of second magnetoresistive effect elements arranged in the entire memory chip and function as dummies,
- wherein a sum total of occupying areas of the first and second magnetoresistive effect elements is 5% to 80% of a predetermined area arbitrarily selected from the memory chip.
A method of manufacturing a magnetic memory device having a memory cell portion and a peripheral circuit portion, comprising:
- forming a first metal material film in each of the memory cell portion and the peripheral circuit portion;
- forming a magnetoresistive effect film on the first metal material film in each of the memory cell portion and the peripheral circuit portion;
- forming a cap film on the magnetoresistive effect film in each of the memory cell portion and the peripheral circuit portion;
- forming a first cap layer by patterning the cap film of the memory cell portion into a first shape, and forming a second cap layer by patterning the cap film of the peripheral circuit portion into a second shape;
- forming a first magnetoresistive effect element which functions as a memory element by patterning the magnetoresistive effect film of the memory cell portion into the first shape by using the first cap layer, and
- forming a second magnetoresistive effect element which functions as a dummy by patterning the magnetoresistive effect film of the peripheral circuit portion into the second shape by using the second cap layer;
- forming a first metal layer by patterning the first metal material film of the memory cell portion into a third shape, and forming a second metal layer by patterning the first metal material film of the peripheral circuit portion into a fourth shape;
- forming a first insulating film on the first and second cap layers and the first and second metal layers in each of the memory cell portion and the peripheral circuit portion;
- flattening the first insulating film;
- and
- removing the first insulating film until a surface of the first cap layer is exposed.
Dependencies are inferred from the claim text.