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US 2004/0169213 A1Published application
Integrated circuit and seed layers
AssigneeMicron Technology, Inc.
InventorPaul A. Farrar
Life of this patent
Estimating the term…
Abstract
Structures are provided which improve performance in integrated circuits. The structures include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the integrated circuit. The low energy ion implantation allows for the distinct placement of both the diffusion barrier and the seed layer. Structures are formed with a barrier/adhesion layer deposited in the number of trenches using a low energy ion implantation, e.g. a 100 to 800 electron volt (eV) ion implantation. A seed layer is deposited on the barrier/adhesion layer in the number of trenches also using the low energy ion implantation. Such structures include aluminum, copper, gold, and silver metal interconnects.
Claims79
An integrated circuit comprising:
- a substrate including one or more devices;
- a first insulating layer overlying the substrate having one or more first level vias connecting to the one or more devices in the substrate;
- and
- a second insulating layer overlying the first insulating layer, the second insulating layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including:
- a first level metal line;
- a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of first level vias;
- and
- a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the first level metal line.
5 more elements
An integrated circuit comprising:
- a substrate including one or more devices;
- an insulator layer overlying the substrate, the insulator layer having one or more first level vias connecting to the one or more devices in the substrate;
- and
- a polymer layer overlying the insulator layer, the polyimide layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including:
- a first level metal line;
- a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of first level vias;
- and
- a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the first level metal line.
5 more elements
An integrated circuit comprising:
- a substrate including one or more devices;
- an insulator layer overlying the substrate having one or more first level vias connecting to the one or more transistors in the substrate;
- and
- an oxide layer overlying the insulator layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including:
- a layer of titanium or zirconium having a thickness of approximately 50 Angstroms disposed on a first level via of the number of first level vias;
- a first layer of aluminum on the layer of titanium or zirconium having a thickness of approximately 50 Angstroms;
- a layer of copper on the first layer of aluminum having a thickness of approximately 10 Angstroms;
- and
- a second layer of aluminum on the layer of copper having a thickness of approximately 50 Angstroms.
6 more elements
An integrated circuit comprising:
- a number of first level vias in a first insulator layer connecting to a number of silicon devices in a substrate;
- and
- a first number of conductive structures formed over and connecting to the number of first level vias in the first insulator layer, each conductive structure, each conductive structure of the first number of conductive structures including:
- a layer of zirconium having a thickness of approximately 15 Angstroms disposed on a first level via of the number of first level vias;
- a seed layer of copper on the layer of zirconium having a thickness of approximately 50 Angstroms;
- and
- a copper metal line formed on the seed layer of copper;
- and
- a polymer layer surrounding the first number of conductive structures.
6 more elements
An integrated circuit comprising:
- a number of first level vias in a first insulator layer connecting to a number of silicon devices in a substrate;
- a first number of conductive structures formed over and connecting to the number of first level vias in the first insulator layer, each conductive structure, comprising:
- a first barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms disposed on a first level via of the number of first level vias;
- a first seed layer formed on at least a portion of the barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms;
- and
- a first core conductor formed on the first seed layer;
- a polymer surrounding the first number of conductive structures;
- and
- a second number of conductive structures include a number of second level vias and a number of second level metal lines, wherein the second number of conductive structures are formed over and connect to the first number of conductive structures, and wherein each of the second number of conductive structures includes:
- a second barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms;
- a second seed layer formed on at least a portion of the barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms;
- and
- a second core conductor formed on the second seed layer.
10 more elements
An integrated circuit comprising:
- a number of first level vias in a first insulator layer connecting to a number of transistors in a substrate;
- and
- an oxide layer formed over the number of first level vias in the first insulator layer, wherein the oxide layer includes a number of conductive structures connecting from a top surface of the oxide layer to the number of first level vias, each conductive structure comprising:
- a layer of tantalum nitride having a thickness of approximately 5 to 100 Angstroms disposed on a first level via of the number of first level vias;
- a seed layer of copper on the layer of tantalum nitride having a thickness of approximately 100 Angstroms;
- and
- a copper metal line formed on the seed layer of copper.
4 more elements
An integrated circuit comprising:
- a first level via in a first insulator layer connecting to a transistor in a substrate;
- and
- an oxide layer formed over the first level via in the first insulator layer, wherein the oxide layer includes a conductive structure connecting from a top surface of the oxide layer to the first level via, the conductive structure including:
- a barrier/adhesion layer having two material layers, the barrier/adhesion layer disposed on a first level via of the number of first level vias;
- a seed layer on the barrier/adhesion layer;
- a layer of aluminum on the seed layer, the layer of aluminum having a thickness of about 50 Angstroms;
- and
- a metal line formed on the layer of aluminum.
5 more elements
An integrated circuit comprising:
- a first level via in a first insulator layer connecting to a transistor in a substrate;
- a titanium silicide liner that contains the first level via;
- a conductive structure formed over the first level via in the first insulator layer, the conductive structure including:
- a barrier/adhesion layer disposed on the first level via;
- a seed layer on the barrier/adhesion layer;
- and
- a metal line disposed above the seed layer;
- and
- a second insulator layer containing the conductive structure.
6 more elements
An integrated circuit comprising:
- a first level via in a first insulator layer connecting to a transistor in a substrate;
- a first conductive structure formed over the first level via in the first insulator layer, the first conductive structure including:
- a first barrier/adhesion layer disposed on the first level via;
- a first seed layer disposed on the first barrier/adhesion layer;
- and
- a first metal line disposed above the first seed layer;
- a second insulator layer containing the first conductive structure;
- a second conductive structure having a portion disposed on the first metal line of the first conductive structure, the second conductive structure including:
- a second barrier/adhesion layer disposed on the first metal line;
- a second seed layer disposed on the second barrier/adhesion layer;
- and
- a second metal line disposed above the second seed layer.
9 more elements
An integrated circuit, comprising:
- a first level via in a first insulator layer connecting to a silicon device in a substrate;
- a liner containing the first level via;
- a first conductive structure formed over the first level via in the first insulator layer, the first conductive structure including:
- a first barrier/adhesion layer disposed on the first level via;
- a first seed layer disposed on the first barrier/adhesion layer;
- and
- a first metal line disposed above the first seed layer;
- a second insulator layer containing the first conductive structure;
- a second conductive structure having a portion disposed on the first metal line of the first conductive structure, the second conductive structure including:
- a second barrier/adhesion layer disposed on the first metal line;
- a second seed layer disposed on the second barrier/adhesion layer;
- and
- a second metal line disposed above the second seed layer.
10 more elements
A system, comprising:
- a processor;
- and
- an integrated circuit coupled to the processor, wherein the integrated circuit includes:
- a substrate including one or more devices;
- a first insulating layer overlying the substrate having one or more first level vias connecting to the one or more devices in the substrate;
- and
- a second insulating layer overlying the first insulating layer, the second insulating layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including:
- a first level metal line;
- a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of first level vias;
- and
- a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the first level metal line.
8 more elements
A system, comprising:
- a processor;
- and
- an integrated circuit coupled to the processor, wherein the integrated circuit includes:
- a substrate including one or more transistors;
- an insulator layer overlying the substrate having one or more first level vias connecting to the one or more transistors in the substrate;
- and
- a polyimide layer overlying the insulator layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including:
- a first level metal line;
- a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of first level vias;
- and
- a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the first level metal line.
8 more elements
A system, comprising:
- a processor;
- and
- an integrated circuit coupled to the processor, wherein the integrated circuit includes:
- a substrate including one or more transistors;
- an insulator layer overlying the substrate having one or more first level vias connecting to the one or more transistors in the substrate;
- and
- an oxide layer overlying the insulator layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including:
- a first level metal line;
- a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of first level vias;
- and
- a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the first level metal line.
8 more elements
Dependencies are inferred from the claim text.