Avoiding shorting in capacitors
AssigneeInfineon Technologies AG
InventorsHaoren Zhuang, Ulrich Egger, Jingyu Lian, Gerhard Beitel, Karl Hornik
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Abstract
A capacitor structure having a capacitor with a top electrode, a bottom electrode, and a capacitor dielectric layer between the top and bottom electrodes is disclosed. The capacitor comprises an upper and lower portion. The demarcation between the upper and lower portion is located between top and bottom surfaces of the capacitor dielectric layer. A dielectric layer is provided on the sidewalls of the upper portion of the capacitor to prevent shorting between the electrodes that can be caused by a conductive fence formed during processing.
Claims19
A capacitor structure comprising:
- a capacitor including
- a top electrode,
- a bottom electrode,
- a capacitor dielectric layer between the top and bottom electrodes,
- wherein the capacitor includes an upper and a lower portion, the upper and lower portion whose demarcation is between top and bottom surfaces of the capacitor dielectric layer;
- and
- a dielectric layer covering capacitor sidewalls in the upper portion of the capacitor.
A method of forming a capacitor structure comprising:
- providing a substrate prepared layers of a capacitor including a bottom electrode layer, a capacitor dielectric layer, and top electrode layer;
- depositing a mask layer over the layers of the capacitor;
- patterning the mask layer to form a mask, exposing portions of the layers of the capacitor;
- etching the expose portions of the capacitor layers to form an upper portion of the capacitor, wherein a demarcation of the upper portion of the capacitor is between top and bottom surfaces of the capacitor dielectric layer;
- forming dielectric spacers covering the sidewalls of the upper portion of the capacitor;
- and
- continue patterning the capacitor layers to form the lower portion of the capacitor.
Dependencies are inferred from the claim text.