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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChang-Ming Dai, Chung-Hsing Chang, Jan-Wen You, Burn J. Lin
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A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is ¼ to ½ the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.
A method of processing data for defining a layer in an integrated circuit which is outputted to form a set of phase and trim masks comprising:
A method for producing phase shifting layout data by a command script system that applies alt-PSM design rules, OPC, scattering bar rules, and gate blocking area generation comprising:
A method for simultaneously producing a gate feature and an interconnect feature in an integrated circuit which have linewidths smaller than can be achieved by conventional methods comprising:
A method of forming a feature on a substrate that includes a first exposure with an alternating phase shift mask with full size scattering bars and a second exposure with a tritone attenuated mask having at least one scattering bar, said scattering bars are not printed in the resulting pattern from the lithography process.
Dependencies are inferred from the claim text.