Service programmable logic arrays with low tunnel barrier interpoly insulators

A method for forming an in service programmable logic array, comprising:

• forming a plurality of input lines for receiving an input signal;
• forming a plurality of output lines;
• and
• forming one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein forming the first logic plane and the second logic plane forming a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal, wherein forming each logic cell includes forming a vertical non-volatile memory cell including:
• forming a vertical pillar extending outwardly from a semiconductor substrate at intersections of the input lines and interconnect lines and at the intersections of the interconnect lines and the output lines, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region;
• forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
• forming a number of control gates opposing the floating gates;
• and
• forming a low tunnel barrier intergate insulator to separate the control gate from the floating gate
• forming a number of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first source/drain regions of column adjacent pillars in the array.

A method for operating an in-server programmable logic array, comprising:

• writing to one or more floating gates of a number of non-volatile memory cells in one or more arrays using channel hot electron injection, the one or more arrays having a first logic plane and a second logic plane connected between a number of input lines and a number of output lines, wherein number of non-volatile memory cells in the first logic plane and the second logic plane are arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal on the input lines, wherein each non-volatile memory cell includes:
• a first source/drain region and a second source/drain region separated by a channel region in a substrate;
• a floating gate opposing the channel region and separated therefrom by a gate oxide;
• a control gate opposing the floating gate;
• and
• wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator;
• erasing charge from one or more floating gates by tunneling electrons off of the floating gate and onto the control gate.

A method for operating an in-server programmable logic array, comprising:

• writing to one or more floating gates of a number of non-volatile memory cells in one or more arrays using channel hot electron injection, the one or more arrays having a first logic plane and a second logic plane connected between a number of input lines and a number of output lines, wherein number of non-volatile memory cells in the first logic plane and the second logic plane are arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal on the input lines, wherein each non-volatile memory cell includes:
• a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region;
• a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
• a number of control gates opposing the floating gates;
• a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of non-volatile memory cells;
• a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of non-volatile memory cells, wherein the number of control gates lines are separated from the floating gates by a low tunnel barrier intergate insulator;
• and
• a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of non-volatile memory cells;
• and
• erasing charge from the one or more floating gates by tunneling electrons off of the one or more floating gates and onto the number of control gates.