Method of designing semiconductor integrated circuit with accurate capacitance extraction
AssigneeFujitsu Limited
InventorsShinichi Kurose, Kenji Kumagai
Life of this patent
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Abstract
A semiconductor integrated circuit includes a block having a first border edge on which an external connection terminal is provided and a second border edge on which no external connection terminal is provided, a wiring prohibited area which extends a first distance from the first border edge and in which no wiring line running parallel to the first border edge exists, and a shielding line which is at a second distance from the second border edge and runs parallel to the second border edge.
Claims16
A semiconductor integrated circuit, comprising:
- a block having a first border edge on which an external connection terminal is provided and a second border edge on which no external connection terminal is provided;
- a wiring prohibited area which extends a first distance from the first border edge and in which no wiring line running parallel to the first border edge exists;
- and
- a shielding line which is at a second distance from the second border edge and runs parallel to the second border edge.
A method of designing a semiconductor integrated circuit, comprising the steps of:
- a) checking each border edge of a block area so as to determine whether a border edge is a first border edge where an external connection terminal is provided or a second border edge where no external connection terminal is provided;
- b) providing a wiring prohibited area which extends a first distance from the first border edge and in which no wiring line running parallel to the first border edge exists;
- and
- c) providing a shielding line which is at a second distance from the second border edge and runs parallel to the second border edge.
Dependencies are inferred from the claim text.