US 2004/0168140 A1 · Method for analyzing path delays in an IC clock tree

Abstract

A macro-cell is incorporated into an integrated circuit (IC) design to describe a fixed arrangement of cells to be included in the IC. The IC includes a clock tree for delivering a clock signal from its root to all clocked devices (sinks) within the IC external to the macro-cell, and to a root of a clock tree subtree included within the macro-cell for delivering the clock signal from its root to sinks residing within the macro-cell. A model of the subtree depicts the maximum and minimum delays of the clock signal's rising and falling edges between the subtree root and the sinks within the macro-cell as functions of the clock signal's rising and falling edge transition times as they arrives at the subtree root and also as functions of the relative amount of delay the rising and falling edges experience as they pass from the clock tree root to the subtree root. A clock tree synthesis tool uses the subtree model to determine the maximum and minimum rising and falling edge path delays though the subtree when estimating the maximum and minimum amounts by which the clock tree delays the clock signal's rising and falling edges as they pass from the clock tree root to any sink of the IC.

Claims19

Dependent claims

A method of processing a layout design for an integrated circuit (IC), wherein the IC comprises a clock tree for delivering a clock signal from a first IC node to a first plurality of sinks within the IC and to a second IC node forming a root of a subtree of the clock tree for delivering the clock signal from the second IC node to a second plurality of sinks within the IC, the method comprising the steps of:

a. providing a model of the subtree for generating estimates of maximum and minimum delays of rising and falling edges of the clock signal from the second IC node to any of the second plurality of sinks, wherein the estimates are functions of a measure of relative magnitudes of delays of rising and falling edges of the clock signal from the first IC node to the second IC node, when said measure is supplied as input to the model;
b. processing the layout design to generate estimates of magnitudes of delays of rising and falling edge of the clock signal between the first IC node and the second IC node and to determine there from the measure of the relative magnitudes of the delays of the rising and falling edges of the clock signal from the first node to the second IC node;
and
c. supplying the measure determined at step c as input to the model such that the model generates the estimates of maximum and minimum delays of rising and falling edges of the clock signal from the second IC node to any of the second plurality of sinks.

1 more element

Computer readable media, which when read an executed by a computer, causes the computer to carry out a method of processing a layout design for an integrated circuit (IC), the IC comprising a clock tree for delivering a clock signal from a first IC node of the IC to a first plurality of sinks within the IC and to a second IC node of the IC forming a root of a subtree of the clock tree that delivers the clock signal from the second IC node to a second plurality of sinks within the method comprises the steps of:

a. processing the layout design to generate estimates of magnitudes of transition times of the rising and falling edges of the clock signal at the second IC node, estimates of magnitudes of delays of rising and falling edges of the clock signal between the first IC node and the second IC node, and a measure of the relative magnitudes of the delays of the rising and falling edges of the clock signal from the first IC node to the second IC node;
and
b. supplying the estimates of the magnitudes of the transition times and the measure of the relative magnitudes of the delays of the rising and falling edges of the clock signal between the first IC node and the second IC node generated at step a as inputs to a model of the subtree which generates estimates of maximum and minimum delays of rising and falling edges of the clock signal from the second IC node to any of the second plurality of sinks as functions of said inputs.

A method of generating and analyzing an integrated circuit (IC) design comprising the steps of:

a. generating a macro-cell comprising a description of a set of clocked devices (sinks) and a clock tree subtree for delivering a clock signal from a root of the subtree to the sinks;
and
b. generating a model of the macro-cell's subtree representing maximum and minimum rising and falling clock signal edge path delays through the subtree between the root of the subtree and the sinks of the macro-cell as functions of the clock signal's rising and falling edge transition times at the root of the clock tree and also as functions of a relationship between delays that the clock signal's rising and falling edges experience relative to one another prior to reaching the root of the subtree.

An apparatus for processing a layout design for an integrated circuit (IC), wherein the IC comprises a clock tree for delivering a clock signal from a first IC node to a first plurality of sinks within the IC and to a second IC node forming a root of a subtree of the clock tree for delivering the clock signal from the second IC node to a second plurality of sinks within the IC, the apparatus comprising:

means for providing a model of the subtree for generating estimates of maximum and minimum delays of rising and falling edges of the clock signal from the second IC node to any of the second plurality of sinks, wherein the estimates are functions of a measure of relative magnitudes of delays of rising and falling edges of the clock signal from the first IC node to the second IC node, when said measure is supplied as input to the model;
means for processing the layout design to generate estimates of magnitudes of delays of rising and falling edge of the clock signal between the first IC node and the second IC node and to determine there from the measure of the relative magnitudes of the delays of the rising and falling edges of the clock signal from the first node to the second IC node;
and
means for supplying the determined measure as input to the model such that the model generates the estimates of maximum and minimum delays of rising and falling edges of the clock signal from the second IC node to any of the second plurality of sinks.

1 more element

Dependencies are inferred from the claim text.

Method for analyzing path delays in an IC clock tree

Life of this patent

Method for analyzing path delays in an IC clock tree

Life of this patent

Abstract

Claims19