Clock gating approach to accommodate infrequent additional processing latencies

Abstract

A processor system has a first device, a clock control circuit and a processor. The first device receives a clock signal, runs a plurality of operations including a lengthy operation requiring more than a single clock cycle to complete, and produces a control signal when the lengthy operation is activated. The clock control circuit receives the clock signal and outputs a gated clock signal only when the first device is not producing the control signal. The processor unit runs off of the gated clock signal. The first device may be a memory, and the lengthy operation may be correction of a soft error in memory. According to a second aspect, the first device requires a longer clock cycle rather than more clock cycles. The clock can be gated to effectively double the period when the lengthy operation is activated.

Dependencies are inferred from the claim text.