US 2004/0168101 A1 · Redundant memory system and memory controller used therefor

Abstract

A redundant memory system makes it possible to replace a failed one of memory modules incorporated with a new memory sub-module during the energized or in-service state even if the OS used in a system does not support the memory redundancy function. This memory system includes memory modules inserted into respective slots, and a memory controller connected to the slots and providing redundancy. The controller defines one of the modules as a parity memory and its remainder as data memories. A first parity code is generated from desired data to be stored and written into the parity memory while the desired data are written into the respective data memories. The desired data are read from the respective data memories and the first parity code is read from the parity memory to thereby conduct a parity check operation and an error correction operation of the desired data using the desired data and the first parity code, resulting in the redundancy.

Claims10

Dependent claims

A redundant memory system comprising:

memory slots;
memory modules for storing data, the modules being inserted into the respective slots;
and
a memory controller connected to the slots and providing redundancy;
wherein the controller defines one of the modules as a parity memory and its remainder as data memories;
and wherein a first parity code is generated from desired data to be stored and written into the parity memory and the desired data are written into the respective data memories;
and wherein the desired data are read from the respective data memories and the first parity code is read from the parity memory to thereby conduct a parity check operation and an error correction operation of the desired data using the desired data and the first parity code, resulting in the redundancy.

4 more elements

A redundant memory system comprising:

n memory slots, where n is an integer greater than one;
n memory modules for storing data, the modules being inserted into the respective slots;
and
a memory controller connected to the slots and providing redundancy;
wherein the controller comprises
n ECC/ChIPKILL circuits connected to the respective slots, for ECC code generation, error check, data reconfiguration, and ChipKill operation;
a parity-generation/check/reconfiguration circuit connected to the n ECC/CHIPKILL circuits, the parity-generation/check/reconfiguration circuit defining one of the n modules as a parity memory and its remainder as (n−1) data memories;
wherein a first parity code is generated from desired data to be stored and written into the parity memory while the desired data are written into the respective (n−1) data memories;
and wherein a second parity code is generated from the desired data read from the (n−1) data memories and compared with the first parity code read from the parity memory, thereby conducting an error checking operation;
and wherein when one of the (n−1) data memories is failed, the desired data is reconfigured using the first parity code and the (n−2) data memories other than the failed one;
and
an error count circuit including a generation counter register for storing generation counts of FCC errors and ChipKill errors, and a comparator for comparing the generation counts with a threshold;
wherein the comparator outputs an interrupt signal to the upper system when one of the generation counts exceeds the threshold.

10 more elements

A memory controller comprising:

n ECC/ChIPRILL circuits connected to respective n memory slots, for ECC code generation, error check, data reconfiguration, and ChipKill operation, where n is an integer greater than one;
a parity-generation/check/reconfiguration circuit connected to the n ECC/CHIPKILL circuits, the parity-generation/check/reconfiguration circuit defining one of n memory modules as a parity memory and its remainder as (n−1) data memories;
wherein a first parity code is generated from desired data to be stored and written into the parity memory while the desired data are written into the respective (n−1) data memories;
and wherein a second parity code is generated from the desired data read from the (n−1) data memories and compared with the first parity code read from the parity memory, thereby conducting an error checking operation;
and wherein when one of the (n−1) data memories is failed, the desired data is reconfigured using the first parity code and the (n−2) data memories other than the failed one;
and
an error count circuit including a generation counter register for storing generation counts of ECC errors and ChipKill errors, and a comparator for comparing the generation counts with a threshold;
wherein the comparator outputs an interrupt signal to the upper system when one of the generation counts exceeds the threshold.

5 more elements

Dependencies are inferred from the claim text.

Redundant memory system and memory controller used therefor

Life of this patent

Redundant memory system and memory controller used therefor

Life of this patent

Abstract

Claims10